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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features up to 400 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring wide range of operating voltages. see operating conditions on page 20 qualified for automotive applications. see automotive products on page 65 168-ball csp_bga or 176-lead lqfp with exposed pad memory 116k bytes of on-chip memory external memory controller wi th glueless support for sdram and asynchronous 8-bit and 16-bit memories optional 4m bit spi flash with boot option flexible booting options from internal spi flash, otp memory, external spi/parallel memories, or from spi/uart host devices code security with lockbox secure technology one-time-programmable (otp) memory memory management unit providing memory protection peripherals ieee 802.3-compliant 10/100 ethernet mac with ieee 1588 support (adsp-bf518/adsp-bf518f only) parallel peripheral interface (ppi), supporting itu-r 656 video data formats 2 dual-channel, fu ll-duplex synchronous serial ports (sports), supporting 8 stereo i 2 s channels 12 peripheral dmas, 2 mastered by the ethernet mac 2 memory-to-memory dmas with external request lines event handler with 56 interrupt inputs 2 serial peripheral interfaces (spi) removable storage interface (rsi) controller for mmc, sd, sdio, and ce-ata 2 uarts with irda support 2-wire interface (twi) controller eight 32-bit timers/counters with pwm support 3-phase 16-bit center-based pwm unit 32-bit general-purpose counter real-time clock (rtc) and watchdog timer 32-bit core timer 40 general-purpose i/os (gpios) debug/jtag interface on-chip pll capable of frequency multiplication jtag test and emulation peripheral access bus otp 3-phase pwm watchdog timer rtc twi sport1-0 rsi (sdio) ppi uart1C0 spi0 4 mbit spi flash (see table 1) spi1 timer7C0 counter emac boot rom dma external bus interrupt controller dma controller l1 data memory l1 instruction memory 16 dma core bus external access bus external port flash, sdram control ports b
rev. b | page 2 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table of contents features ................................................................. 1 memory ................................................................ 1 peripherals ............................................................. 1 revision history ...................................................... 2 general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 blackfin processor core .......................................... 3 memory architecture ............................................ 5 event handling .................................................... 6 dma controllers .................................................. 7 processor peripherals ............................................. 7 dynamic power management ................................ 11 voltage regulation interface .................................. 13 clock signals ..................................................... 13 booting modes ................................................... 14 instruction set description ................................... 15 development tools ............................................. 15 designing an emul ator-compatible processor board (target) ................................... 16 related documents ............................................. 16 related signal chains ........................................... 16 lockbox secure technology disclaimer .................... 16 signal descriptions ................................................. 17 specifications ........................................................ 20 operating conditions ........................................... 20 electrical characteristics ....................................... 22 flash memory characteristics ................................ 24 absolute maximum ratings ................................... 25 package information ............................................ 26 esd sensitivity ................................................... 26 timing specifications ........................................... 27 output drive currents ......................................... 50 test conditions .................................................. 52 thermal characteristics ........................................ 56 176-lead lqfp lead assignment . .............................. 57 168-ball csp_bga ball assignment .. ......................... 60 outline dimensions ................................................ 63 surface-mount design .......................................... 64 automotive products .............................................. 65 ordering guide ..................................................... 65 revision history 1/11rev. a to rev. b this data sheet release coincides with the release of the revised adsp-bf51x blackfin processor hardware reference. all redundant information has been removed. revised several specifications in operating conditions ... 20 revised f vco specification in phase-locked loop operating conditions ........................................................... 21 revised several specifications in electrical characteristics 22 added additional f ckin specification for automotive models in clock and reset timing .......................................... 27 changed the parameter v ddmem to v ddext in asynchronous memory read cycle timing ..................................... 29 sdram interface timing ........................................ 31 parallel peripheral interface timing ........................... 33 serial ports ........................................................... 37 revised t hfspe specification in parallel peripheral interface tim- ing ..................................................................... 33 revised t hfspe specification and added the t psud specification in parallel peripheral interface timing ........................... 33 revised the t wl and t wh specifications in rsi controller timing ............................................ 35 revised t wl , t wh and t oh specification in rsi controller timing (high speed mode) ................................................. 36 revised t mdcih and t mdcoh specifications in 10/100 ethernet mac controller timing: mii station management ........ 48 corrected dimensions in 168-ball chip scale package ball grid array [csp_bga] (bc-168-1) ................................... 64
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 3 of 68 | january 2011 general description the adsp-bf512/adsp-bf512f, adsp-bf514/adsp- bf514f, adsp-bf516/adsp-bf516f, adsp-bf518/adsp- bf518f processors are members of the blackfin ? family of prod- ucts, incorporating the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processi ng engine, the advantages of a clean, orthogonal risc-like micr oprocessor instruction set, and single-instruction, multiple-dat a (simd) multimedia capabili- ties into a single instruction-set architecture. the processors are completely code compatible with other blackfin processors. by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of oper ation to significantl y lower overall power consumption. this capability can result in a substantial reduc- tion in power consum ption, compared with just varying the frequency of operation. this a llows longer battery life for portable appliances. system integration the adsp-bf51x processors are highly integrated system-on-a- chip solutions for the next generation of embedded network connected applications. by combining industry-standard inter- faces with a high performance signal processing core, cost- effective applications can be developed quickly, without the need for costly external comp onents. the system peripherals include an ieee-compliant 802. 3 10/100 ethernet mac with ieee-1588 support (adsp-bf518/ad sp-bf518f only), an rsi controller, a twi controller, tw o uart ports, two spi ports, two serial ports (sports), nine general-purpose 32-bit timers (eight with pwm capability), 3-phase pwm for motor control, a real-time clock, a watchdog timer, and a parallel peripheral interface (ppi). blackfin processor core as shown in figure 1 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit da ta from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. the compare/select and vector search instructions are also provided. table 1. processor comparison feature adsp-bf512 adsp-bf512f adsp-bf514 adsp-bf514f adsp-bf516 adsp-bf516f adsp-bf518 adsp-bf518f ieee-1588 CCCCCC11 ethernet mac CCCC1111 rsi CC111111 twi 11111111 sports 22222222 uarts 22222222 spis 22222222 gp timers 88888888 watchdog timers 11111111 rtc 11111111 ppi 11111111 internal 4mbit spi flash C1C1C1C1 rotary counter 11111111 3-phase pwm pairs 33333333 gpios 40 40 40 40 40 40 40 40 memory (bytes) l1 instruction sram 32k l1 instruction sram/cache 16k l1 data sram 32k l1 data sram/cache 32k l1 scratchpad 4k l3 boot rom 32k maximum speed grade 400 mhz package options 176-lead lqfp with exposed pad 168-ball csp_bga
rev. b | page 4 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f for certain instructions, two 16- bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issu e capability, where a 32-bit figure 1. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 5 of 68 | january 2011 instruction can be issued in parallel with two 16-bit instruc- tions, allowing the programmer to use many of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf51x processors view memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low- latency on-chip memory as cache or sram, and larger, lower-co st and performance off-chip memory systems. the memory ma p for both internal and exter- nal memory space is shown in figure 2 . the on-chip l1 memory system is the highest-performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 132m bytes of physical memory. the memory dma controller prov ides high bandwidth data- movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the adsp-bf51x processors have three blocks of on-chip memory that provide high bandwidth access to the core. the first block is the l1 instruction memory, consisting of 48k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of up to two banks of up to 32k bytes each. each memory bank is configurable, offering both cache and sram functional- ity. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the sdram controller can be prog rammed to interface to up to 128m bytes of sdram. a separa te row can be open for each sdram internal bank, and the sdram controller supports up to four internal sdram banks, improving overall performance. the asynchronous memory cont roller can be programmed to control up to four banks of devi ces with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguo us if each is fully populated with 1m byte of memory. flash memory the adsp-bf512f/ads p-bf514f/adsp-bf516f/ adsp-bf518f processors contain a spi flash memory within the package of the processor and connected to spi0. the spi flash memory has a 4m bit capacity and 1.8v (nominal) operating voltage. the prog ram/erase endurance is 100,000 cycles per block, and this memo ry has greater than 100 years of data retention capability. also included are support for software write protection and for fast erase and byte-program. figure 2. adsp-bf51x inte rnal/external memory map reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sram (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram / cache (16k bytes) data bank b sram (16k bytes) data bank a sram / cache (16k bytes) asyncmemorybank3(1mbytes) asyncmemorybank2(1mbytes) asyncmemorybank1(1mbytes) asyncmemorybank0(1mbytes) instruction bank c sram/cache (16k bytes) in t er n a l m e mo r y m a p e x t e r na l m e m o r y m a p 0xffff ffff 0x ffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 data bank a sram (16k bytes) 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 8000 instruction bank a sram (16k bytes) reserved boot rom (32k bytes) 0xef00 8000 reserved 0x08 00 0000 0xffa0 4000 sdram memory (16m bytes - 128m bytes)
rev. b | page 6 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f the processors internally connec t to the flash memory die with the spi0sck, spi0sel4 or ph8, spi0mosi, and spi0miso sig- nals similar to an external spi flash. to further provide a secure processing environment, these in ternally connected signals are not exposed outside of the pack age. for this reason, program- ming the adsp-bf51xf flash memo ry is performed by running code on the processor andcannot be programmed from external signals. data transfers between the spi flash and the processor cannot be probed externally. the flash memory has the follow- ing additional features ? serial interface architecturespi compatible with mode 0 and mode 3 ? superior reliabilityendurance of 100,000 cycles and greater than 100 years data retention ? flexible erase capabilityuni form 4k byte sectors and uniform 32 and 64k byte overlay blocks ? fast erase and byte-program chip-erase time = 125 ms (typical), sector-/block-erase time = 62 ms (typical) byte- program time = 50 s (typical) ? auto address increment ( aai) programmingdecreases total chip programming time over byte-program operations ? end-of-write detectionsoftware polling the busy bit in status register, busy st atus readout on so pin ? software write protectionw rite protection through block-protection bits in status register one-time programmable memory the processors have 64k bits of one-time programmable non- volatile memory that can be pr ogrammed by the developer only once. it includes the array and logic to support read access and programming. additionally, its pages can be write protected. the otp memory allows both public and private data to be stored on-chip. in addition to storing public and private key data for applications requiring security, otp allows developers to store completely user-definab le data such as customer id, product id, and mac address. therefore, generic parts can be supplied which are then progra mmed and protected by the developer within this non-volatile memory. i/o memory space the processors do not define a se parate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control re gisters mapped into memory- mapped registers (mmrs) at ad dresses near the top of the 4g byte address space. these ar e separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting from rom the processors contain a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. if the processors are configured to boot from boot rom memory space, the pro- cessor starts executing from th e on-chip boot rom. for more information, see booting modes on page 14 . event handling the event controller handles all asynchronous and synchronous events to the processor. the pr ocessors provide event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures th at servicing of a higher priority event takes precedence over servicing of a lower priority event. the controller provides support for five different types of events: ? emulationan emulation even t causes the processor to enter emulation mode, allowing command and control of the processor through the jtag interface. ? resetthis event resets the processor. ? nonmaskable interrupt (n mi)the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptionsevents that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. conditions such as data alignment violations and undefined instructions cause exceptions. ?interruptsevents that occu r asynchronously to program flow. they are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the event controller consists of two stages, the core event con- troller (cec) and the system in terrupt controller (sic). the core event controller works with the system interrupt controller to prioritize and control all sy stem events. conceptually, inter- rupts from the peripherals ente r into the sic, and are then routed directly into the general-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripheral s of the processors. the inputs to the cec, identifies their names in the event vector table (evt), and lists their priori ties are described in the adsp-bf51x blackfin processo r hardware reference manual system interrupts chapter.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 7 of 68 | january 2011 system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processors provid e a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (sic_iarx). see the adsp-bf51x blackfin processor hardware reference manual system interrupts chapter for the inputs into the sic and the default mappings into the cec. the sic allows further control of event processing by providing three pairs of 32-bit interrupt cont rol and status re gisters. each register contains a bit correspond ing to each of the peripheral interrupt events. for more information, see the adsp-bf51x blackfin processor hard ware reference manual system inter- rupts chapter. dma controllers the adsp-bf51x processors have multiple independent dma channels that support automated data transfers with minimal overhead for the processor co re. dma transfers can occur between the processor's internal memories and any of its dma- capable peripherals. additiona lly, dma transfers can be accom- plished between any of the dma-capable peripherals and external devices connected to th e external memory interfaces, including the sdram controller and the asynchronous mem- ory controller. dma-capable peri pherals include the ethernet mac, rsi, sports, spis, uarts, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the processors dma controlle r supports both one-dimen- sional (1-d) and two-dimensio nal (2-d) dma transfers. dma transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2-d dma capability suppor ts arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 3 2k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video applications where data can be de- interleaved on the fly. examples of dma types suppo rted by the dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing bu ffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a linked list of descriptors ?2-d dma using an array of desc riptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels that transfer data between the vari- ous memories of the processor sy stem. this enables transfers of blocks of data between any of the memoriesincluding external sdram, rom, sram, and flash memorywith minimal pro- cessor intervention. memory dm a transfers can be controlled by a very flexible descriptor-b ased methodology or by a stan- dard register-based autobuffer mechanism. the processors also have an external dma controller capability via dual external dma request signals when used in conjunc- tion with the external bus interface unit (ebiu). this functionality can be used when a high speed interface is required for external fifos and high bandwidth communica- tions peripherals. it allows co ntrol of the number of data transfers for memory dma. the nu mber of transfers per edge is programmable. this feature can be programmed to allow mem- ory dma to have an increased priority on the external bus relative to the core. processor peripherals the adsp-bf51x processors cont ain a rich set of peripherals connected to the core via severa l high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see figure 1 on page 4 ). the processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexi- ble management of interrupts fr om the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the proces- sor and system to many application scenarios. all of the peripherals, except fo r the general-purpose i/o, rotary counter, twi, three-phase pwm, real-time clock, and timers, are supported by a flexible dma structure. there are also sepa- rate memory dma channels dedicated to data transfers between the processor's variou s memory spaces, including external sdram and asynchronous memory. multiple on-chip buses provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time , stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the proces- sors. the rtc peripheral has a de dicated power suppl y so that it can remain powered up and clocke d even when the rest of the processor is in a low power state. the rtc provides several pro- grammable interrupt options, in cluding interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or inte rrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day.
rev. b | page 8 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wakeup event. additionally, an rtc wakeup ev ent can wake up the processor from deep sleep mode or cause a transition from the hibernate state. connect rtc signals rtxi and rtxo with external compo- nents as shown in figure 3 . watchdog timer the adsp-bf51x processors include a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system avai lability by forcing the proces- sor to a known state through gene ration of a hardware reset, nonmaskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the program- mer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the programmed value. this prot ects the system from remain- ing in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the system clock (sclk) at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the adsp-bf51x proce ssors. eight timers have an external sig- nal that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be sync hronized to an external clock input to the several other associ ated pf signals, an external clock input to the ppi_clk input signal, or to the internal sclk. the timer units can be used in conjunction with the two uarts to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operatin g system periodic interrupts. 3-phase pwm the processors integrate a flexible and programmable 3-phase pwm waveform generator that ca n be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac inductio n (acim) or permanent magnet synchronous (pmsm) motor cont rol. in addition, the pwm block contains special functions that considerably simplify the generation of the required pw m switching patterns for control of the electronically commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for switched reluctan ce motors (srm). features of the 3-phase pwm generation unit are: ? 16-bit center-based pwm generation unit ? programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ? twos-complement implementa tion which permits smooth transition to full on and full off states ? possibility to sync hronize the pwm generation to an exter- nal synchronization ? special provisions for bdcm operation (crossover and output enable functions) ? wide variety of special switched reluctance (sr) operating modes ? output polarity and clock gating control ? dedicated asynchronous pwm shutdown signal general-purpose (gp) counter a 32-bit gp counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or man- ual thumb wheels. the counter can also operate in general- purpose up/down count modes. th en, count direction is either controlled by a level-sensitive input signal or by two edge detectors. figure 3. external components for rtc rtxo c1 c2 x1 suggested components: x1 = ecliptek ec38j (through-hole package) or epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 9 of 68 | january 2011 a third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three signals have a programmable debouncing circuit. an internal signal forwarded to the gp timer unit enables one timer to measure the intervals between count events. boundary registers enable auto-zero operat ion or simple system warning by interrupts when programmabl e count values are exceeded. serial ports the adsp-bf51x processors inco rporate two dual-channel syn- chronous serial ports (sport 0 and sport1) for serial and multiprocessor communications. the sports support the fol- lowing features: serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ? multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ?left-justified mode serial peripheral interface (spi) ports the processors have two spi-co mpatible ports (spi0 and spi1) that enable the processor to communicate with multiple spi- compatible devices. the spi interface uses three sign als for transferring data: two data signals (master output-slave inputCmosi, and master input-slave outputCmiso) and a clock signal (serial clockCsck). an spi chip select input signal (spixss ) lets other spi devices select the processor, and multiple spi chip select output signals let the processor select other spi devices. the spi select signals are reconfigured general-purpose i/o signals. using these signals, the spi port provides a full-duplex, syn- chronous serial interface, whic h supports both master/slave modes and multimaster environments. the spi port baud rate and cloc k phase/polarities are program- mable, and it has an integrated dma channel, configurable to support transmit or receive data streams. the spis dma chan- nel can only service unidirection al accesses at any given time. uart ports the processors provide two full -duplex universa l asynchronous receiver/transmitter (uart) port s, which are fully compatible with pc-standard uarts. each uart port provides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. a uart port includes suppo rt for five to eight data bits, and none, even, or odd parity. op tionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminates by one, one and a half, two or two and a half stop bits. the uart ports support automa tic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmable assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. 2-wire interface (twi) the processors include a twi mo dule for providing a simple exchange method of control data between multiple devices. the twi is compatible with the widely used i 2 c ? bus standard. the twi module offers the capabiliti es of simultaneous master and slave operation, support for both 7-bit addressing and multime- dia data arbitration. the twi interface utilizes two signals for transferring clock (scl) and da ta (sda) and supports the pro- tocol at speeds up to 400k bits /sec. the twi interface signals are compatible with 5 v logic levels. additionally, the proc essors twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. removable storage interface (rsi) the rsi controller, availabl e on the adsp-bf514, adsp- bf516, adsp-bf518, and adsp-bf518f acts as the host inter- face for multi-media cards (mmc), secure digital memory cards (sd card), secure digital input/output cards (sdio), and ce- ata hard disk drives. the followi ng list describes the main fea- tures of the rsi controller. ? support for a single mmc, sd memory, sdio card or ce- ata hard disk drive ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit and 8-bit mmc modes ? support for 4-bit and 8-bit ce-ata hard disk drives ? a ten-signal external interf ace with clock, command, and up to eight data lines ? card detection using one of the data signals ? card interface clock generation from sclk ? sdio interrupt and read wait features ? ce-ata command completion signal recognition and disable
rev. b | page 10 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f 10/100 ethernet mac the adsp-bf516/adsp-bf516f and adsp- bf518/adspbf518f processors offer the capability to directly connect to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset ( 100m bits/sec) operation. the 10/100 ethernet mac peripheral on the processor is fully com- pliant to the ieee 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by th e rest of the processor system. some standard features are: ? support of mii and rmii pr otocols for external phys ? full duplex and half duplex modes ? data framing and encapsulation: generation and detection of preamble, length padding, and fcs ? media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision frames and of back-off timing ? flow control (in full-duplex operation): generation and detection of pause frames ? station management: generation of mdc/mdio frames for read-write access to phy registers ? operating range for active and sleep operating modes, see table 43 on page 45 and table 44 on page 46 ? internal loopback from transmit to receive some advanced features are: ? buffered crystal output to ex ternal phy for support of a single crystal system ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes support even 32-bit alignment of encapsulated rece ive or transmit ip packet data in memory after the 14-byte mac header ? programmable ethernet event interrupt supports any com- bination of: ? selected receive or transmit frame status conditions ? phy interrupt condition ? wakeup frame detected ? selected mac management counter(s) at half-full ? dma descriptor error ? 47 mac management statistics counters with selectable clear-on-read behavi or and programmable interrupts on half maximum value ? programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, uni- cast, control, and damaged frames ? advanced power management supporting unattended transfer of receive and transm it frames and status to/from external memory via dma during low power sleep mode ? system wakeup from sleep operating mode upon magic packet or any of four user-d efinable wakeup frame filters ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ? in rmii operation, seven unused signals may be config- ured as gpio signals for other purposes ieee 1588 support the ieee 1588 standard is a pr ecision clock synchronization protocol for networked measurement and control systems. the adsp-bf518/adsp-bf518f proce ssors include hardware sup- port for ieee 1588 with an integr ated precision time protocol synchronization engine (ptp_tsync). this engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between ptp nodes. the main features of the ptp_sync engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? hardware assisted ti me stamping capable of up to 12.5 ns resolution ? lock adjustment ? programmable ptm message support ? dedicated interrupts ? programmable alarm ? multiple input clock sources (sclk, mii clock, external clock) ? programmable pulse per second (pps) output ? auxiliary snapshot to time stamp external events ports because of the rich set of periph erals, the processors group the many peripheral signals to four portsport f, port g, port h, and port j. most of the associated pins/balls are shared by multi- ple signals. the ports functi on as multiplexer controls. general-purpose i/o (gpio) the adsp-bf51x processors ha ve 40 bidirectional, general- purpose i/o (gpio) signals allocated across three separate gpio modulesportfio, portgio, and porthio, associ- ated with port f, port g, and port h, respectively. each gpio-capable signal shares functionality with other peripherals via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output nor input drivers are active by default. each general-pur- pose port signal can be individu ally controlled by manipulation of the port control, stat us, and interrupt registers.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 11 of 68 | january 2011 parallel peripheral interface (ppi) the adsp-bf51x processors prov ide a parallel peripheral inter- face (ppi) that can co nnect directly to para llel analog-to-digital and digital-to-analog conver ters, itu-r-601/656 video encod- ers and decoders, and other gene ral-purpose peripherals. the ppi consists of a dedicated input clock signal, up to three frame synchronization signals, an d up to 16 data signals. in itu-r-656 modes, the ppi receiv es and parses a data stream of 8-bit or 10-bit data elements. on-chip decode of embedded preamble control and synchronization information is supported. three distinct itu-r- 656 modes are supported: ? active video only modethe ppi does not read in any data between the end of active video (eav) and start of active video (sav) preamble sy mbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. ? vertical blanking only modet he ppi only transfers verti- cal blanking interval (vbi) data, as well as horizontal blanking information and control byte sequences on vbi lines. ? entire field modethe entire incoming bitstream is read in through the ppi. this includ es active video, control pre- amble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. though not explicitly supported, itu-r-656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data ou t the ppi in a frame sync-less mode. the processors 2-d dma feat ures facilitate this transfer by allowing the static frame buff er (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. the general-purpose modes of th e ppi are intended to suit a wide variety of data capture an d transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data transfer per ppi_clk cycle: ? data receive with internally generated frame syncs ? data receive with externally generated frame syncs ? data transmit with internally generated frame syncs ? data transmit with externally generated frame syncs these modes support adc/dac connections, as well as video communication with hardware signalling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. code security with lockbox secure technology a security system consisting of a blend of hardware and soft- ware provides customers with a flexible and rich set of code security features with lockbox ? secure technology. key features include: ? otp memory ? unique chip id ? code authentication ? secure mode of operation the security scheme is based up on the concept of authentica- tion of digital signatures usin g standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. dynamic power management the adsp-bf51x processors pr ovide four operating modes, each with a different performanc e/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. when configured for a 0 v core supply voltage, the processor enters the hibernate state. control of clocking to each of the processor peripherals also reduces power consumption. see table 2 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not real ized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. table 2. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. b | page 12 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc ac tivity wakes up the processor. when in the sleep mode, assertin g wakeup causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled , the processor transitions to the full on mode. if bypass is enabled, the processor transi- tions to the active mode. system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the proces- sor to transition to the acti ve mode. assertion of reset while in deep sleep mode causes the pr ocessor to transition to the full on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the pr ocessor core (cclk) and system blocks (sclk). any critical information stored internally (for example memory contents, register contents) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserve d. writing b#00 to the freq bits in the vr_ctl register also ca uses the ext_wake signal to transition low, which can be used to signal an external voltage regulator to shut down. since v ddext is still supplied in this mode, all of the external sig- nals three-state, unless otherwis e specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. the ethernet module can signal an external regulator to wake up using the ext_wake signal. if pf15 does not connect as a phyint signal to an external phy device, it can be pulled low by any other device to wake the processor up. the processor can also be woken up by a real-time clock wakeup event or by assert- ing the reset pin. all hibernate wakeup events initiate the hardware reset sequence. individual sources are enabled by the vr_ctl register. the ext_wake signal is provided to indi- cate the occurrence of wakeup events. with the exception of the vr_c tl and the rtc registers, all internal registers and memories lose their content in the hiber- nate state. state variables may be held in external sram or sdram. the sckelow bit in the vr_ctl register controls whether or not sdram operates in self-refresh mode, which allows it to retain its content while the processor is in hiberna- tion and through the subsequent reset sequence. power savings as shown in table 3 , the processors support up to six different power domains, which maximizes flexibility while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from the rt c and other i/o, the processor can take advantage of dynamic power management without affecting the rtc or other i/o devices. there are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate specifications table for processor operating conditions; even if the fea- ture/peripheral is not used. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, these power sa vings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. where the variables in the equations are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage table 3. power domains power domain v dd range all internal logic, except rtc, memory, otp v ddint rtc internal logic and crystal i/o v ddrtc memory logic v ddmem otp logic v ddotp optional internal flash v ddflash all other i/o v ddext power savings factor f cclkred f cclknom -------------------------- v ddintred v ddintnom ------------------------------- - ?? ?? 2 t red t nom -------------- - ? ? ? ? = % power savings 1 po wer savings factor ? () 100% =
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 13 of 68 | january 2011 t nom is the duration running at f cclknom t red is the duration running at f cclkred voltage regulation interface the adsp-bf51x processors requir e an external voltage regula- tor to power the v ddint domain. to reduce standby power consumption in the hibernate state, the external voltage regula- tor can be signaled through ext_wake to remove power from the processor core. the ext_wake signal is high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. the power good (pg ) input signal allows the processor to start only after the internal voltage has reached a chosen level. in this way, the startup time of the external regulator is detected after hibernation. for a complete description of the pg functionality, refer to the adsp-bf51x blackfin proc essor hardware reference . clock signals the adsp-bf51x processors can be clocked by an external crys- tal, a sine wave input, or a buffe red, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processor clkin signal. when an external clock is used, the xtal pin/ball must be left unconnected. alternatively, because the processor includes an on-chip oscilla- tor circuit, an external crysta l may be used. for fundamental frequency operation, us e the circuit shown in figure 4 . a paral- lel-resonant, fundamental freq uency, microprocessor-grade crystal is connected across the clkin and xtal pins/balls. the on-chip resistance between th e clkin pin/ball and the xtal pin/ball is in the 500 k range. further parallel resistors are typ- ically not recommended. the two capacitors and the series resistor shown in figure 4 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 4 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 4 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the analog devices website ( www.analog.com )use site search on ee-168. the clkbuf signal is an output signal, which is a buffered ver- sion of the input clock. this signal is particularly useful in ethernet applications to limit the number of required clock sources in the system. in this type of application, a single 25 mhz or 50 mhz crystal may be applied directly to the pro- cessor. the 25 mhz or 50 mhz output of clkbuf can then be connected to an external ethe rnet mii or rmii phy device. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 5 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmab le 5 to 64 multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 6, but it can be modified by a software instruction sequence. on-the-fly frequency changes can be done simply by writing to the pll_div register. the maximum allowed cclk and sclk rates depend on the applied voltages v ddint , v ddext , and v ddmem , and the vco is always permitted to run up to the fre- quency specified by the parts speed grade. the clkout signal reflects the sclk frequency to th e off-chip world. it belongs to the sdram interface, but it functions as a reference signal in other timing specifications as well. while active by default, it can be disabled using the ebiu_sdgctl and ebiu_amgctl registers. figure 4. external crystal connections figure 5. frequency mo dification methods clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18 pf should be treated as a maximum, and the suggested resistor value should be reduced to 0 . 18 pf * en 18 pf * 330 * blackfin 560 pll 5 to 64 1to15 1,2,4,8 vco clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk
rev. b | page 14 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 4 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 5 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the part's speed grade (see page 65 ), it also depends on the applied v ddint voltage. see table 9 for details. the maximal system clock rate (sclk) depends on the chip package and the applied v ddint , v ddext , and v ddmem voltages (see table 11 on page 21 ). booting modes the processor has several mechanisms (listed in table 6 ) for automatically loading internal and external memory after a reset. the boot mode is defined by three bmode input bits dedicated to this purpose. ther e are two catego ries of boot modes. in master boot modes the processor actively loads data from parallel or serial memories . in slave boot modes the pro- cessor receives data from external host devices. the boot modes listed in table 6 provide a number of mecha- nisms for automatically loading the proce ssors internal and external memories after a reset. by default, all boot modes use the slowest meaningful configuration settings. default settings can be altered via the initialization code feature at boot time or by proper otp programming at pre-boot time. the bmode bits of the reset configuration register, sampled during power- on resets and software-initiat ed resets, implement the modes shown in table 6 . ? idle/no boot mode (bmode = 0x0)in this mode, the processor goes into idle. the idle boot mode helps recover from illegal operating modes, such as when the user has mis configured the otp memory. ? boot from 8-bit or 16-bit external flash memory (bmode = 0x1)in this mode, the boot kernel loads the first block header from ad dress 0x2000 0000 anddepend- ing on instructions containing in the headerthe boot kernel performs 8-bit or 16-bit boot or starts program exe- cution at the address provided by the header. by default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle r/w access times, 4-cycle setup). the ardy is not enabled by default, but it can be enabled by otp programming. similarly, all interface behavior and timings can be customized by otp programming. this includes activation of burst-mode or page-mode operation. in this mode, all signals be longing to the asynchronous interface are enabled at the port muxing level. ? boot from internal spi memory (bmode = 0x2)the processor uses the internal ph8 gpio signal to load code previously loaded to the 4 mbit internal spi flash con- nected to spi0. only avai lable on the adsp-bf512f/ adsp-bf514f/adsp-bf516f/adsp-bf518f. ? boot from external spi eeprom or flash (bmode = 0x3)8-bit, 16-bit, 24-bit or 32-bit address- able devices are supported. the processor uses the pg15 gpio signal (at spi0sel2 ) to select a single spi eeprom/flash device connected to the spi0 interface; then submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24- , or 32-bit addressable device is detected. pull-up resistors are required on the ssel and miso signals. by default, a value of 0x85 is written to the spi0_baud register. ? boot from spi0 host device (bmode = 0x4)the proces- sor operates in spi slave mode and is configured to receive the bytes of the ldr file from an spi host (master) agent. in the host, the hwait signal must be interrogated by the table 4. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0010 2:1 100 50 0110 6:1 300 50 1010 10:1 400 40 table 5. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 table 6. booting modes bmode2C0 description 000 idle - no boot 001 boot from 8- or 16-bit external flash memory 010 boot from internal spi memory 011 boot from external spi memory (eeprom or flash) 100 boot from spi0 host 101 boot from otp memory 110 boot from sdram 111 boot from uart0 host
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 15 of 68 | january 2011 host before every transmitted byte. a pull-up resistor is required on the spi0ss input. a pull-down on the serial clock may improve signal quality and booting robustness. ? boot from otp memory (bmode = 0x5)this provides a stand-alone booting method. the boot stream is loaded from on-chip otp memory. by default the boot stream is expected to start from otp pa ge 0x40 on and can occupy all public otp memory up to page 0xdf. this is 2560 bytes. since the start page is programmable the maximum size of the boot stream ca n be extended to 3072 bytes. ? boot from sdram (bmode = 0x6)this is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. the sdram is expe cted to contain a valid boot stream and the sdram cont roller must be configured by the otp settings. ? boot from uart0 host (bmode = 0x7)using an auto- baud handshake sequence, a boot-stream formatted program is downloaded by the host. the host selects a bit rate within the uart clocking capabilities. when performing the autoba ud, the uart expects a @ (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the rx0 sign al to determine the bit rate. the uart then replies with an acknowledgement com- posed of 4 bytes (0xbfthe value of uart0_dll and 0x00the value of uart0_dlh). the host can then download the boot stream. to hold off the host the blackfin processor signals the host with the boot host wait (hwait) signal. therefore, the host must monitor hwait before every transmitted byte. for each of the boot modes, a 16- byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the address stored in the evt1 register. prior to booting, the pre-boot routine interrogates the otp memory. individual boot modes can be customized or even dis- abled based on otp programming. external hardware, especially booting hosts may watch the hwait signal to deter- mine when the pre-boot has finish ed and the boot kernel starts the boot process. by programming otp memory, the user can instruct the preboot routine to also customize the pll, the sdram controller, and the asynchronous interface. the boot kernel differentiates be tween a regular hardware reset and a wakeup-from-hibernate even t to speed up booting in the later case. bits 6-4 in the syst em reset configuration (syscr) register can be used to bypass pre-boot ro utine and/or boot ker- nel in case of a software reset. th ey can also be used to simulate a wakeup-from-hibernate boot in the software reset case. the boot process can be further customized by initialization code. this is a piece of code that is loaded and executed prior to the regular application boot. typically, this is used to configure the sdram controller or to sp eed up booting by managing pll, clock frequencies, wait states, or serial bit rates. the boot rom also features c-callable function entries that can be called by the user application at run time. this enables sec- ond-stage boot or boot ma nagement schemes to be implemented with ease. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction in structions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple le vels of access to core processor resources. the assembly language, which ta kes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mc u features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit macs or four 8-bit alus plus two load/store plus two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16-bit and 32-bit instru ctions (no mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the adsp-bf51x processors are supported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++? devel- opment environment. the same emulator hardware that supports other blackfin processors also fully emulates the adsp-bf51x processors. for mo re information about develop- ment tools, visit www.analog.com . ez-kit lite evaluation board for evaluation of the processors, use the ez-kit lite ? board being developed by analog devices. the board comes with on- chip emulation capabilities and is equipped to enable software development. multiple daughter cards are available.
rev. b | page 16 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog devi ces has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access th e internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the processor must be halted to se nd data and commands, but once an operation has been completed by the emulator, the processor system is set running at fu ll speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (ee-68) analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. related documents the following publications th at describe the adsp-bf512/ adsp-bf514/adsp-bf516/adsp -bf518 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f blackfin processor hardware reference ? adsp-bf53x/bf56x blackfin processor programming reference ? adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f blackfin processor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques lockbox secure technology disclaimer analog devices products contai ning lockbox secure technol- ogy are warranted by analog devi ces as detailed in the analog devices standard terms and conditions of sale. to our knowl- edge, the lockbox secure technolo gy, when used in accordance with the data sheet and hardwa re reference manual specifica- tions, provides a secure method of implementing code and data safeguards. however, analog devices does not guarantee that this technology provides abso lute security. accordingly, analog devices hereby disclaims any and all express and implied warr anties that the lock- box secure technology cannot be breached, compromised, or otherwise circumvented and in no event shall analog devices be liable for any loss, damage, destruction, or release of data, information, physic al property, or intel- lectual property.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 17 of 68 | january 2011 signal descriptions the processors signal definitions are listed in table 7 . in order to maintain maximum function and reduce package size and signal count, some signals have dual, multiplexed functions. in cases where signal function is re configurable, the default state is shown in plain text, while the al ternate function is shown in italics. all pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchro- nous and synchronous memory control, and the buffered xtal output pin (clkbuf). on the external memory interface, the control and address lines are driv en high, with the exception of clkout, which toggles at the sy stem clock rate. during hiber- nate all outputs are three-stated unless otherwise noted in table 7 . all i/o signals have their input buffers disabled with the excep- tion of the signals noted in the data sheet that need pull-ups or pull downs if unused. the sda (serial data) and scl (serial clock) pins/balls are open drain and therefore require a pu llup resistor. consult version 2.1 of the i 2 c specification for the proper resistor value. it is strongly advised to use the available ibis models to ensure that a given board design meet s overshoot/undershoot and sig- nal integrity requirements. if no ibis simulation is performed, it is strongly recommended to add se ries resistor terminations for all driver types a, c and d. th e termination re sistors should be placed near the processor to reduce transients and improve signal integrity. the resistance value, typically 33 or 47 , should be chosen to match the average board trace impedance. additionally, adding a paralle l termination to clkout may prove useful in further enhancing signal integrity. be sure to verify overshoot/undershoot and si gnal integrity specifications on actual hardware. table 7. signal descriptions signal name type function driver type 1 ebiu addr19C1 o address bus a data15C0 i/o data bus a abe1C0 / sdqm1C0 o byte enable or data mask a ams1C0 o asynchronous memory bank selects (require pull-ups if hibernate is used) a are o asynchronous memory read enable a awe o asynchronous memory write enable a sras o sdram row address strobe a scas o sdram column address strobe a swe osdram write enable a scke o sdram clock enable (requires a pull-do wn if hibernate with sdram self-refresh is used) a clkout o sdram clock output b sa10 o sdram a10 signal a sms o sdram bank select a port f: gpio and multiplexed peripherals pf0/ etxd2 / ppi d0 / spi1sel2 / taclk6 i/o gpio/ ethernet mii transmit d2 / ppi data 0 / spi1 slave select 2 / timer6 alternate clock c pf1/ erxd2 / ppi d1 / pwm ah / taclk7 i/o gpio/ ethernet mii receive d2 / ppi data 1 / pwm ah output / timer7 alternate clock c pf2/ etxd3 / ppi d2 / pwm al i/o gpio/ ethernet transmit d3 / ppi data 2 / pwm al output c pf3/ erxd3 / ppi d3 / pwm bh / taclk0 i/o gpio/ ethernet mii data receive d3 / ppi data 3 / pwm bh output / timer0 alternate clock c pf4/ erxclk / ppi d4 / pwm bl / taclk1 i/o gpio/ ethernet mii receive clock / ppi data 4 / pwm bl out / timer1 alternate clk c pf5/ erxdv / ppi d5 / pwm ch / taci0 i/o gpio/ ethernet mii receive data valid / ppi data 5 / pwm ch out / timer0 alternate capture input c pf6/ col / ppi d6 / pwm cl / taci1 i/o gpio/ ethernet mii collision / ppi data 6 / pwm cl out / timer1 alternate capture input c pf7/ spi0sel1 / ppi d7 / pwmsync i/o gpio/ spi0 slave select 1 / ppi data 7 / pwm sync c
rev. b | page 18 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f pf8/ mdc /ppi d8/ spi1sel4 i/o gpio/ ethernet management channel clock / ppi data 8 / spi1 slave select 4 c pf9/ mdio / ppi d9 / tmr2 i/o gpio/ ethernet management channel serial data / ppi data 9 / timer 2 c pf10/ etxd0 / ppi d10 / tmr3 i/o gpio/ ethernet mii or rmii transmit d0/ppi data 10 / timer 3 c pf11/ erxd0 / ppi d11 / pwm ah / taci3 i/o gpio/ ethernet mii receive d0/ppi data 11 / pwm ah output / timer3 alternate capture input c pf12/ etxd1 / ppi d12 / pwm al i/o gpio/ ethernet mii transmit d1 / ppi data 12 / pwm al output c pf13/ erxd1 / ppi d13 / pwm bh i/o gpio/ ethernet mii or rmii receive d1 / ppi data 13 / pwm bh output c pf14/ etxen / ppi d14 / pwm bl i/o gpio/ ethernet mii transmit enable / ppi data 14 / pwm bl out c pf15 2 / rmii phyint / ppi d15 / pwm_synca i/o gpio/ ethernet mii phy interrupt / ppi data 15 / alternate pwm sync c port g: gpio and multiplexed peripherals pg0/ miicrs / rmiicrs / hwait 3 / spi1sel3 i/o gpio/ ethernet mii or rmii carrier sense or rmii data valid / hwait / spi1 slave select3 c pg1/ erxer / dmar1 / pwm ch i/o gpio/ ethernet mii or rmii receive error / dma req 1 / pwm ch out c pg2/ miitxclk / rmiiref_clk / dmar0 / pwm cl i/o gpio/ ethernet mii or rmii reference clock / dma req 0 / pwm cl out c pg3/ dr0pri / rsi_data0 / spi0sel5 / taclk3 i/o gpio/ sport0 primary rx data / rsi data 0 / spi0 slave select 5 / timer3 alternate clk c pg4/ rsclk0 / rsi_data1 / tmr5 / taci5 i/o gpio/ sport0 rx clock / rsi data 1 / timer 5 / timer5 alternate capture input d pg5/ rfs0 / rsi_data2 / ppiclk / tmrclk i/o gpio/ sport0 rx frame sync / rsi data 2 / ppi clock / external timer reference c pg6/ tfs0 / rsi_data3 / tmr0 / ppifs1 i/o gpio/ sport0 tx frame sync / rsi data 3 / timer0 / ppi frame sync1 c pg7/ dt0pri / rsi_cmd / tmr1 / ppifs2 i/o gpio/ sport0 tx primary data / rsi command / timer 1 / ppi frame sync2 c pg8/ tsclk0 / rsi_clk / tmr6 / taci6 i/o gpio/ sport0 tx clock / rsi clock / timer 6 / timer6 alternate capture input d pg9/ dt0sec / uart0tx / tmr4 i/o gpio/ sport0 secondary tx data / uart0 transmit / timer 4 c pg10/ dr0sec / uart0rx / taci4 i/o gpio/ sport0 secondary rx data / uart0 receive / timer4 alternate capture input c pg11/ spi0ss / ams2 / spi1sel5 / taclk2 i/o gpio/ spi0 slave device select / asynchronous memory bank select 2 / spi1 slave select 5 / timer2 alternate clk c pg12/ spi0sck / ppiclk / tmrclk / ptp_pps i/o gpio/ spi0 clock/ppi clock / external timer reference / ptp pulse per second out d pg13/ spi0miso 4 / tmr0 / ppifs1 / ptp_clkout i/o gpio/ spi0 master in slave out/timer0 / ppi frame sync1 / ptp clock out c pg14/ spi0mosi / tmr1 / ppifs2 / pwm trip / ptp_auxin i/o gpio/ spi0 master out slave in / timer 1 / ppi frame sync2/pwm trip / ptp auxiliary snapshot trigger input c pg15/ spi0sel2 / ppifs3 / ams3 i/o gpio/ spi0 slave select 2 / ppi frame sync3 / asynchronous memory bank select 3 c port h: gpio and mu ltiplexed peripherals ph0/ dr1pri / spi1ss / rsi_data4 i/o gpio/ sport1 primary rx data / spi1 device select / rsi data 4 c ph1/ rfs1 / spi1miso / rsi_data5 i/o gpio/ sport1 rx frame sync / spi1 master in slave out / rsi data 5 c ph2/ rsclk1 / spi1sck / rsi data6 i/o gpio/ sport1 rx clock / spi1 clock / rsi data 6 d ph3/ dt1pri / spi1mosi / rsi data7 i/o gpio/ sport1 primary tx data / spi1 master out slave in / rsi data 7 c ph4/ tfs1 / aoe / spi0sel3 / cud i/o gpio/ sport1 tx frame sync / asynchronous memory output enable / spi0 slave select 3 / counter up direction c ph5/ tsclk1 / ardy / ptp_ext_clkin / cdg i/o gpio/ sport1 tx clock / asynchronous memory ha rdware ready control / external clock for ptp tsync / counter down gate d ph6/ dt1sec / uart1tx / spi1sel1 / czm i/o gpio/ sport1 secondary tx data / uart1 transmit / spi1 slave select 1 / counter zero marker c ph7/ dr1sec / uart1rx / tmr7 / taci2 i/o gpio/ sport1 secondary rx data / uart1 receive / timer 7 / timer2 alternate clock input c table 7. signal descriptions signal name type function driver type 1
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 19 of 68 | january 2011 port j pj0:scl i/o 5v twi serial clock (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) e pj1:sda i/o 5v twi serial data (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) e real time clock rtxi i rtc crystal input (this ball should be pulled low when not used.) rtxo o rtc crystal output (does not three-state during hibernate) jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this signal should be pulled low if the jtag port is not used.) emu o emulation output c clock clkin i clock/crystal input xtal o crystal output (if clkbuf is enabled, does not three-state during hibernate) clkbuf o buffered xtal output (if enabled, does not three-state during hibernate) c mode controls reset i reset nmi i non-maskable interrupt (this signal should be pulled high when not used.) bmode2-0 i boot mode strap 2-0 voltage regulation interface pg i power good (this signal should be pulled low when not used.) ext_wake o wake up indication (does not three-state during hibernate) c power supplies all supplies must be powered see operating conditions on page 20 . v ddext pi/o power supply v ddint p internal power supply v ddrtc p real time clock power supply v ddflash p internal spi flash power supply v ddmem pmem power supply v ppotp p otp programming voltage v ddotp potp power supply gnd g ground for all supplies 1 see output drive currents on page 50 for more information about each driver type. 2 when driven low, the pf15 signal can be used to wake up the pr ocessor from the hibernate state, either in normal gpio mode or i n ethernet mode as phyint . if the pin/ball is used for wake up, enable the feature with the phywe bit in the vr_ctl register, and pull-up the signal with a resistor. 3 boot host wait is a gpio s ignal toggled by the boot kernel. the mandatory external pull-up/pull-down resistor defines the signa l polarity. 4 a pull-up resistor is required for the boot from external spi eeprom or flash (bmode = 0x3). table 7. signal descriptions signal name type function driver type 1
rev. b | page 20 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f specifications note that component specificat ions are subject to change without notice. operating conditions parameter conditions min nominal max unit v ddint internal supply voltage industrial models 1.14 1.47 v internal supply voltage commercial models 1.10 1.47 v internal supply voltage automotive models 1.33 1.47 v v ddext 1, 2 1 must remain powered (even if the as sociated function is not used). 2 v ddext is the supply to the gpio. external supply voltage 1.8 v i/o, nonautomotive models 1.7 1.8 1.9 v external supply voltage 2.5 v i/o, nonautomotive models 2.25 2.5 2.75 v external supply voltage 3.3 v i/o, all models 3.0 3.3 3.6 v v ddmem 3 3 pins/balls that use v ddmem are data15C0, addr19C1, abe1C0 , are , awe , ams1C0 , sa10, swe , scas , clkout, sras , sms , scke. these pins/balls are not tolerant to voltages higher than v ddmem . when using any of the async hronous memory signals ams3C2 , ardy, or aoe v ddmem and v ddext must be shorted externally. mem supply voltage 1.8 v i/o, nonautomotive models 1.7 1.8 1.9 v mem supply voltage 2.5 v i/o, nonautomotive models 2.25 2.5 2.75 v mem supply voltage 3.3 v i/o, all models 3.0 3.3 3.6 v v ddrtc 4 4 if not used, power with v ddext . rtc power supply voltage 2.25 3.6 v v ddflash 4 internal spi flash supply voltage 1.7 1.8 1.9 v v ddotp otp supply voltage 2.25 2.5 2.75 v v ppotp otp programming voltage for reads 1 2.25 2.5 2.75 v for writes 5 5 the v ppotp voltage for writes must only be applied wh en programming otp memory. there is a finite amount of cumulative time that this vol tage may be appl ied (dependent on voltage and junction temperature) over the lifetime of the part. 6.9 7.0 7.1 v v ih high level input voltage 6, 7 6 bidirectional pins/balls (pf15C0, pg15C0, ph7C0) and input pins/balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0) of the adsp-bf51x are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 7 parameter value applies to all input and bi directional pins/balls except sda and scl. v ddext /v ddmem = 1.90 v 1.2 v high level input voltage 6, 7 v ddext /v ddmem = 2.75 v 1.7 v high level input voltage 6, 7 v ddext /v ddmem = 3.6 v 2 v v ihtwi high level input voltage v ddext = 1.90 v/2.75 v/3.6 v 0.7 x v bustwi v bustwi 8 8 the v ihtwi min and max value vary with the selection in the twi_dt field of the nongpio_drive register. see v bustwi min and max values in table 8 . v v il low level input voltage 6, 7 v ddext /v ddmem = 1.7 v 0.6 v low level input voltage 6, 7 v ddext /v ddmem = 2.25 v 0.7 v low level input voltage 6, 7 v ddext /v ddmem = 3.0 v 0.8 v v iltwi low level input voltage v ddext = minimum 0.3 x v bustwi 9 9 sda and scl are pulled up to v bustwi . see table 8 . v junction temperature 168-ball csp_bga @ t ambient = 0c to +70c 0 +95 c junction temperature 168-ball csp_bga @ t ambient = C40c to +85c C40 +105 c junction temperature 176-lead lqfp @ t ambient = 0c to +70c 0 +95 c junction temperature 176-lead lqfp @ t ambient = C40c to +85c C40 +105 c
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 21 of 68 | january 2011 table 8 shows settings for twi_ dt in the nongpio_drive register. set this register prior to using the twi port. clock related operating conditions table 9 describes the timing requirements for the processor clocks. take care in selecting ms el, ssel, and csel ratios so as not to exceed the maximum co re clock and system clock. table 10 describes phase-locked loop operating conditions. table 8. twi_dt field selections and v ddext /v bustwi twi_dt v ddext nominal v bustwi minimum v bustwi nominal v bustwi maximum unit 000 (default) 3.3 2.97 3.3 3.63 v 001 1.8 1.7 1.8 1.98 v 010 2.5 2.97 3.3 3.63 v 011 1.8 2.97 3.3 3.63 v 100 3.3 4.5 5 5.5 v 101 1.8 2.25 2.5 2.75 v 110 2.5 2.25 2.5 2.75 v 111 (reserved) table 9. core clock (cclk) requirements parameter nominal voltage setting maximum unit f cclk core clock frequency (v ddint =1.33 v minimum, all models) 1.400 v 400 mhz core clock frequency (v ddint =1.23 v minimum, industrial/commercial models) 1.300 v 300 mhz core clock frequency (v ddint = 1.14 v minimum, industrial models only) 1.200 v 200 mhz core clock frequency (v ddint = 1.10 v minimum, commercial models only) 1.150 v 200 mhz table 10. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency (commercial/industrial models) 72 instruction rate 1 mhz voltage controlled oscillator (vco) frequency (automotive models) 84 instruction rate 1 mhz 1 for more information, see ordering guide on page 65. table 11. sclk conditions v ddext /v ddmem 1.8 v nominal v ddext /v ddmem 2.5 v or 3.3 v nominal parameter 1 max max unit f sclk clkout/sclk frequency (v ddint 1.230 v minimum) 80 100 mhz f sclk clkout/sclk frequency (v ddint < 1.230 v) 80 80 mhz 1 f sclk must be less than or equal to f cclk and is subject to additional restrict ions for sdram interface operation. see table 28 on page 31 .
rev. b | page 22 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f electrical characteristics parameter test conditions min typical max unit v oh high level output voltage v ddext /v ddmem = 1.7 v, i oh =C0.5ma 1.35 v high level output voltage v ddext /v ddmem = 2.25 v, i oh =C0.5ma 2v high level output voltage v ddext /v ddmem = 3.0 v, i oh =C0.5ma 2.4 v v ol low level output voltage v ddext /v ddmem = 1.7/2.25/3.0 v, i ol =2.0ma 0.4 v i ih 1 high level input current v ddext /v ddmem =3.6 v, v in =3.6v 10 a i il 1 low level input current v ddext /v ddmem =3.6 v, v in = 0 v 10 a i ihp 2 high level input current jtag v ddext = 3.6 v, v in = 3.6 v 75 a i ozh 3 three-state leakage current v ddext /v ddmem = 3.6 v, v in =3.6v 10 a i ozhtwi 4 three-state leakage current v ddext =3.0 v, v in = 5.5 v 10 a i ozl 3 three-state leakage current v ddext /v ddmem = 3.6 v, v in = 0 v 10 a c in 5, 6 input capacitance f in = 1 mhz, t ambient = 25c, v in =2.5v 58 pf c intwi 4, 6 input capacitance f in = 1 mhz, t ambient = 25c, v in =2.5v 15 pf i dddeepsleep 7 v ddint current in deep sleep mode v ddint = 1.3 v, f cclk = 0 mhz, f sclk =0mhz, t j = 25c, asf = 0.00 2.1 ma i ddsleep v ddint current in sleep mode v ddint = 1.3 v, f sclk = 25 mhz, t j = 25c 5.5 ma i dd-idle v ddint current in idle v ddint = 1.3 v, f cclk = 50 mhz, f sclk =25mhz, t j = 25c, asf = 0.41 12 ma i dd-typ v ddint current v ddint = 1.3 v, f cclk = 300 mhz, f sclk =25mhz, t j = 25c, asf = 1.00 77 ma i dd-typ v ddint current v ddint = 1.4 v, f cclk = 400 mhz, f sclk =25mhz, t j = 25c, asf = 1.00 108 ma i ddhibernate 8 hibernate state current v ddext =v ddmem =v ddrtc =3.30 vv ddotp =v ppotp =2.5 v, t j = 25c, clkin = 0 mhz @ t j = 25c 40 a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 a i ddsleep 8, 9 v ddint current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz table 13 + (0.20 v ddint f sclk ) ma 10 i dddeepsleep 8, 10 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 13 ma
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 23 of 68 | january 2011 total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 22 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 13 ), and i ddint specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (v ddint ) and frequency ( table 14 ). there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf) which represents application code runn ing on the processor core and l1 memories ( table 12 ). the asf is combined with the cclk frequency and v ddint dependent data in table 14 to calculate this part. the second part is due to transistor switch ing in the system clock (sclk) domain, which is included in the i ddint specification equation. i ddint 10, 11 v ddint current f cclk > 0 mhz, f sclk 0 mhz table 13 + ( table 14 asf) + (0.20 v ddint f sclk ) ma i ddflash1 flash memory supply current 1 asynchronous read 10 6 ma i ddflash2 flash memory supply current 2 standby 412 a i ddflash3 flash memory supply current 3 program and erase 11 16 ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory read 2ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory write 2ma i ppotp v ppotp current v ppotp = 2.5 v, t j = 25c, otp memory read 100 a i ppotp v ppotp current v ppotp = table 19 v, t j = 25c, otp memory write 3ma 1 applies to input balls. 2 applies to jtag input balls (tck, tdi, tms, trst) . 3 applies to three-statable balls. 4 applies to bidirection al balls scl and sda. 5 applies to all signal ba lls, except scl and sda. 6 guaranteed, but not tested. 7 see the adsp-bf51x blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 8 includes current on v ddext , v ddmem , v ddotp , and v ppotp supplies. clock inputs are tied high or low. 9 guaranteed maximum specifications. 10 unit for v ddint is v (volts). unit for f sclk is mhz. 11 see table 12 for the list of i ddint power vectors covered. parameter test conditions min typical max unit table 12. activity scaling factors (asf) 1 1 see estimating power for a sdp-bf534/bf536/bf537 blackfin processors (ee-297) . the power vector information al so applies to the adsp-bf51x processors. i ddint power vector activity scaling factor (asf) i dd-peak 1.29 i dd-high 1.25 i dd-typ 1.00 i dd-app 0.85 i dd-nop 0.70 i dd-idle 0.41
rev. b | page 24 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f flash memory characteristics table 13. static currenti dd-deepsleep (ma) t j (c) 1 voltage (v ddint ) 1 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v C40 0.9 1.0 1.0 1.1 1.1 1.2 1.3 1.7 1.9 C20 1.0 1.1 1.2 1.3 1.4 1.6 1.7 1.9 2.0 0 1.2 1.3 1.4 1.6 1.8 2.0 2.2 2.3 2.5 25 1.8 1.9 2.1 2.3 2.5 2.8 3.1 3.3 3.7 40 2.4 2.6 2.8 3.0 3.3 3.7 4.0 4.4 4.9 55 3.3 3.5 3.8 4.3 4.6 5.0 5.5 6.1 6.7 70 4.6 5.0 5.4 6.0 6.4 7.0 7.7 8.4 9.2 85 6.5 7.1 7.7 8.3 9.1 9.9 10.8 11.8 12.8 100 9.2 10.0 10.8 11.7 12.7 13.7 15.0 16.1 17.5 105 10.3 11.1 12.1 13.1 14.2 15.3 16.6 18.0 19.4 1 valid frequency and voltage ra nges are model-specific. see operating conditions on page 20 . table 14. dynamic current in cclk domain (ma, with asf = 1.0) 1 f cclk (mhz) 2 voltage (v ddint ) 2 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v 400 n/a n/a n/a n/a 93.4 97.7 102.1 106.5 111.0 350 n/a n/a n/a n/a 82.4 86.2 90.1 94.0 98.0 300 n/a n/a 64.8 68.1 71.4 74.7 78.1 81.5 85.0 250 n/a n/a 54.8 57.5 60.4 63.2 66.1 69.0 71.9 200 40.2 42.5 44.7 47.0 49.4 51.7 54.1 56.5 58.9 150 31.1 32.9 34.7 36.5 38.4 40.2 42.1 44.0 45.9 100 22.0 23.4 24.7 26.0 27.4 28.7 30.1 31.5 33.0 1 the values are not guaranteed as standalone maximum specifications. they must be com bined with static current per the equations of electrical characteristics on page 22 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions on page 20 . table 15. reliability characteristics parameter min units test method n end endurance 100,000 cycles jedec standard a117 t dr data retention 100 years jedec standard a103 table 16. ac operating characteristics parameter min max units f clk 1 serial clock frequency 25 mhz t se sector-erase 75 ms t be block-erase 75 ms t sce chip-erase 150 ms t bp 2 byte-program 60 s 1 maximum clock frequency for read instruction, 0x03, is 20 mhz. 2 aai-word program tbp maximum specificatio n is also at 60 s maximum time.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 25 of 68 | january 2011 absolute maximum ratings stresses greater than those listed in table 17 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. when programming otp memory on the adsp-bf51x proces- sor, the v ppotp pin/ball must be set to th e write value specified in the operating conditions on page 20 . there is a finite amount of cumulative time that the write voltage may be applied (dependent on voltage and junction temperature) to v ppotp over the lifetime of the part. ther efore, maximum otp memory pro- gramming time for the processor is shown in table 19 . table 20 and table 21 specify the maximum total source/sink (i oh /i ol ) current for a group of pins. permanent damage can occur if this value is exceeded. to understand this specification, if pins pf9, pf8, pf7, pf 6, and pf5 from group 1 in table 21 table were sourcing or sinking 2 ma each, the total current for those pins would be 10 ma. this would allow up to 70 ma total that could be sourced or sunk by the remaining pins in the group without damaging the device. note that the v oh and v ol specifications have separate per-pin maximum current require- ments as shown in the electrical characteristics table. table 17. absolute maximum ratings parameter rating internal supply voltage (v ddint ) C0.3 v to +1.50 v external (i/o) supply voltage (v ddext /v ddmem ) C0.3 v to +3.8 v input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 18 . 2 applies only when v ddext is within specifications. when v ddext is outside speci- fications, the range is v ddext 0.2. C0.5 v to +3.6 v input voltage 1, 3 3 applies to signals scl, sda. C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext /v ddmem +0.5 v i oh /i ol current per pin group 4 4 for more information, see the information preceding table 20 and table 21 . 80 ma (max) storage temperature range C65c to +150c junction temperature while biased +110c table 18. maximum duty cycle for input transient voltage 1 1 applies to all signal pins/balls wi th the exception of clkin, xtal. v in min (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. v in max (v) 2 maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. the is equivalent to the meas ured duration of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.50 +3.80 100% C0.70 +4.00 40% C0.80 +4.10 25% C0.90 +4.20 15% C1.00 +4.30 10% table 19. maximum otp memory programming time temperature vppotp voltage (v) 25c 85c 110c 6.9 6000 sec 100 sec 25 sec 7.0 2400 sec 44 sec 12 sec 7.1 1000 sec 18 sec 4.5 sec table 20. total current pin groupsCv ddmem groups group pins in group 1 data15, data14, data13, data12, data11, data10 2 data9, data8, data7, data6, data5, data4 3 data3, data2, data1, data0, addr19, addr18 4 addr17, addr16, addr15, addr14, addr13 5 addr12, addr11, addr10, addr9, addr8, addr7 6 addr6, addr5, addr4, addr3, addr2, addr1 7abe1 , abe0 , sa10, swe , scas , sras 8sms , scke, ams1 , are , awe , ams0 , clkout table 21. total current pin groupsCv ddext groups group pins in group 1 pf9, pf8, pf7, pf6, pf5, pf4, pf3, pf2 2 pf1, pf0, pg15, pg14, pg13, pg12, pg11, pg10 3 pg9, pg8, pg7, pg6, pg5, pg4, pg3, pg2, bmode0, bmode1, bmode2 4pg1, pg0, tdo, emu , tdi, tck, trst , tms 5reset , nmi , clkbuf 6 ph7, ph6, ph5, ph4, ph3, ph2, ph1, ph0 7 pf15, pf14, pf13, pf12 , pf11, sda, scl, pf10
rev. b | page 26 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f package information the information presented in figure 6 and table 22 provides details about the package branding for the processor. for a com- plete listing of prod uct availability, see ordering guide on page 65 . esd sensitivity figure 6. product information on package table 22. package br and information brand key field description adsp-bf51x product name t temperature range pp package type z lead free option ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliance designator yyww date code vvvvvv.x n.n tppzccc adsp-bf51x a b #yyww country_of_origin esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 27 of 68 | january 2011 timing specifications clock and reset timing table 23 and figure 7 describe clock and reset operations. per the cclk and sclk timing specifications in table 9 , table 10 , and table 11 on page 21 , combinations of clkin and clock multipliers must not select core/p eripheral clocks in excess of the processors speed grade. table 23. clock and reset timing parameter min max unit timing requirement s f ckin clkin frequency (commercial/industrial models 1, 2, 3, 4 12 50 mhz f ckin clkin frequency (automotive models) 1, 2, 3, 4 14 50 mhz t ckinl clkin low pulse 1 10 ns t ckinh clkin high pulse 1 10 ns t wrst reset asserted pulse width low 5 11 t ckin ns switching characteristic t bufdlay clkin to clkbuf delay 11 ns 1 applies to pll bypass mode and pll nonbypass mode. 2 combinations of the clkin frequency and the p ll clock multiplier must not exceed the allowed f vco , f cclk , and f sclk settings discussed in table 9 through table 11 on page 21 . 3 the t ckin period (see figure 7 ) equals 1/f ckin . 4 if the df bit in the pll_ctl register is set, the minimum f ckin specification is 24 mhz for commercial/industri al models and 28 mhz for automotive models. 5 applies after power-up se quence is complete. see table 24 and figure 8 for power-up reset timing. figure 7. clock and reset timing table 24. power-up reset timing parameter min max unit timing requirement s t rst_in_pwr reset deasserted after the v ddint , v ddext , v ddrtc , v ddmem , v ddotp , and clkin pins are stable and within specification 3500 t ckin ns clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset clkbuf
rev. b | page 28 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f flash reset timing driving the reset pin low resets the flash device. driving the reset pin high puts the device in normal operating mode. the so pin is in high impedance state while the device is in reset. a successful reset will reset the status register to its power-up state. see table 25 for default power-up modes. a device reset during an active program or erase operation aborts the operation and data of the targeted address range may be co rrupted or lost due to the aborted erase or program operation. the device exits aai programming mode in progress an d places the so pin in high impedance state. figure 8. power-up reset timing reset t rst_in_pwr clkin v dd_supplies table 25. reset timing parameter min max unit timing requirements t recr reset recovery from read 100 ns t recp reset recovery from program 10 s f rece reset recovery from erase 1ms figure 9. flash reset timing sck rst t recr t recp t rece ce
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 29 of 68 | january 2011 asynchronous memory read cycle timing table 26. asynchronous memory read cycle timing v ddmem 1.8v nominal v ddmem 2.5 v/3.3v nominal parameter min max min max unit timing requirements t sdat data15C0 setup before clkout 2.1 2.1 ns t hdat data15C0 hold after clkout 1.2 0.8 ns t sardy ardy setup before clkout 4 4 ns t hardy ardy hold after clkout 0.2 0.2 ns switching characteristic s t do output delay after clkout 1 1 output pins/balls include ams3C0 , abe1C0 , addr19C1, aoe , are . 66ns t ho output hold after clkout 1 0.8 0.8 ns figure 10. asynchronous memory read cycle timing t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t hardy t sardy t sdat t hdat t sardy clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
rev. b | page 30 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f asynchronous memory write cycle timing table 27. asynchronous memory write cycle timing parameter min max unit timing requirements t sardy ardy setup before clkout 4 ns t hardy ardy hold after clkout 0.2 ns switching characteristic s t ddat data15C0 disable after clkout 6 ns t endat data15C0 enable after clkout 0 ns t do output delay after clkout 1 1 output pins/balls include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6ns t ho output hold after clkout 1 0.8 ns figure 11. asynchronous memory write cycle timing setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe ardy data 15C0 t sardy t sardy t ddat t endat t hardy t ho t do t hardy
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 31 of 68 | january 2011 sdram interface timing table 28. sdram interface timing v ddmem 1.8v nominal v ddmem 2.5 v/3.3v nominal parameter min max min max unit timing requirement s t ssdat data setup before clkout 1.5 1.5 ns t hsdat data hold after clkout 1.3 0.8 ns switching characteristics t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 11 on page 21 . package type and reduced supply voltages affect the best-case value listed here. 12.5 10 ns t sclkh clkout width high 5 4 ns t sclkl clkout width low 5 4 ns t dcad command, address, data delay after clkout 2 2 command pins/balls include: sras , scas , swe , sdqm, sms , sa10, scke. 54ns t hcad command, address, data hold after clkout 2 11ns t dsdat data disable after clkout 5.5 5 ns t ensdat data enable after clkout 0 0 ns figure 12. sdram interface timing t sclk clkout t sclkl t sclkh t ssdat t hsdat t ensdat t dcad t dsdat t hcad t dcad t hcad data (in) data (out) command, address (out) note: command = sras , scas , swe , sdqm, sms , sa10, scke.
rev. b | page 32 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f external dma request timing table 29 and figure 13 describe the external dma request operations. table 29. external dma request timing 1 v ddmem /v ddext 1.8 v nominal v ddmem /v ddext 2.5 v/3.3 v nominal parameter min max min max unit timing prequirements t dr dmarx asserted to clkout high setup 9 7.2 ns t dh clkout high to dmarx deasserted hold time 0 0 ns t dmaract dmarx active pulse width t sclk + 1 t sclk + 1 ns t dmarinact dmarx inactive pulse width 1.75 t sclk 1.75 t sclk ns 1 because the external dma cont rol pins are part of the v ddext power domain and the clkout signal is part of the v ddmem power domain, systems in which v ddext and v ddmem are not equal may require level sh ifting logic for correct operation. figure 13. external dma request timing clkout t ds dmar0/1 (active low) dmar0/1 (active high) t dmaract t dmarinact t dh
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 33 of 68 | january 2011 parallel peripheral interface timing table 30 and figure 15 on page 33 , figure 21 on page 38 , and figure 24 on page 40 describe parallel peripheral interface operations. table 30. parallel peripheral interface timing v ddext 1.8 v nominal v ddext 2.5 v/3.3 v nominal parameter min max min max unit timing requirements t pclkw ppi_clk width t sclk C 1.5 t sclk C 1.5 ns t pclk ppi_clk period 2 t sclk C 1.5 2 t sclk C 1.5 ns timing requirements - gp input and frame capture modes t psud external frame sync startup delay 1 4 t pclk 4 t pclk ns t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 6.7 ns t hfspe external frame sync hold after ppi_clk 1.75 1.75 ns t sdrpe receive data setup before ppi_clk 4.1 3.5 ns t hdrpe receive data hold after ppi_clk 2 1.6 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 8 8 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 8.2 8 ns t hdtpe transmit data hold after ppi_clk 2.3 1.9 ns 1 the ppi port is fully enabled 4 ppi clock cycles after the pab wr ite to the ppi port enable bit. only after the ppi port is ful ly enabled are external frame syncs and data words guaranteed to be received co rrectly by the ppi peripheral. figure 14. ppi with external frame sync timing figure 15. ppi gp rx mode with external frame sync timing ppi_clk ppi_fs1/2 t psud t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw
rev. b | page 34 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f figure 16. ppi gp tx mode with external frame sync timing figure 17. ppi gp rx mode with internal frame sync timing figure 18. ppi gp tx mode with internal frame sync timing t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 35 of 68 | january 2011 rsi controller timing table 31 and figure 19 describe rsi controller timing. table 32 and figure 20 describe rsi controlle r (high speed) timing. table 31. rsi controller timing parameter min max unit timing requirements t isu input setup time 5.6 ns t ih input hold time 2 ns switching characteristics f pp 1 clock frequency data transfer mode 0 25 mhz f od clock frequency identification mode 100 2 400 khz t wl clock low time 10 ns t wh clock high time 10 ns t tlh clock rise time 10 ns t thl clock fall time 10 ns t odly output delay time during data transfer mode 14 ns t odly output delay time during identification mode 50 ns 1 t pp = 1/f pp 2 specification can be 0 kh z, which means to stop the clock. the given minimum frequency range is for ca ses where a continuous cl ock is required. figure 19. rsi controller timing sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly v oh (min) v ol (max)
rev. b | page 36 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table 32. rsi controller timing (high speed mode) parameter min max unit timing requirements t isu input setup time 5.6 ns t ih input hold time 2 ns switching characteristics f pp 1 clock frequency data transfer mode 0 50 mhz t wl clock low time 7 ns t wh clock high time 7 ns t tlh clock rise time 3ns t thl clock fall time 3ns t odly output delay time during data transfer mode 4 ns t oh output hold time 2.75 ns 1 t pp = 1/f pp figure 20. rsi controller timing (high speed mode) sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly t oh v oh (min) v ol (max)
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 37 of 68 | january 2011 serial ports table 33 through table 36 on page 40 and figure 21 on page 38 through figure 24 on page 40 describe serial port operations. table 33. serial portsexternal clock v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing requirements t sfse 1 tfsx/rfsx setup before tsclkx/rsclkx 3 3 ns t hfse 1 tfsx/rfsx hold after tsclkx/rsclkx 3 3 ns t sdre 1 receive data setup before rsclkx 3 3 ns t hdre 1 receive data hold after rsclkx 3.5 3 ns t sclkew tsclkx/rsclkx width 7 4.5 ns t sclke tsclkx/rsclkx period 2 t sclk 2 t sclk ns t sudte 2 start-up delay from sport enable to first external tfsx 4 t sclke 4 t sclke ns t sudre 2 start-up delay from sport enable to first external rfsx 4 t sclke 4 t sclke ns switching characteristics t dfse 3 tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 10 10 ns t hofse 3 tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 00ns t ddte 3 transmit data delay after tsclkx 10 10 ns t hdte 3 transmit data hold after tsclkx 0 0 ns 1 referenced to sample edge. 2 verified in design but untested. 3 referenced to drive edge. table 34. serial portsinternal clock v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing requirements t sfsi 1 tfsx/rfsx setup before tsclkx/rsclkx 11 9.6 ns t hfsi 1 tfsx/rfsx hold after tsclkx/rsclkx C1.5 C1.5 ns t sdri 1 receive data setup before rsclkx 11 9.6 ns t hdri 1 receive data hold after rsclkx C1.5 C1.5 ns switching characteristics t dfsi 2 tfsx/rfsx delay after tsclkx/r sclkx (internally generated tfsx/rfsx) 33ns t hofsi 2 tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) ? 2 ? 1ns t ddti 2 transmit data delay after tsclkx 3 3 ns t hdti 2 transmit data hold after tsclkx ? 1.8 ? 1.5 ns t sclkiw tsclkx/rsclkx width 10 8 ns 1 referenced to sample edge. 2 referenced to drive edge.
rev. b | page 38 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f figure 21. serial ports figure 22. serial port start up with external clock and frame sync t sdri rsclkx drx t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw t sdre rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 39 of 68 | january 2011 table 35. serial portsenable and three-state 1 parameter min max unit switching characteristics t dtene data enable delay from external tsclkx 0 ns t ddtte data disable delay from external tsclkx t sclk + 1 ns t dteni data enable delay from internal tsclkx C2.0 ns t ddtti data disable delay from internal tsclkx t sclk + 1 ns 1 referenced to drive edge. figure 23. enable and three-state tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
rev. b | page 40 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table 36. external late frame sync v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit switching characteristics t ddtlfse 1, 2 data delay from late external tfsx or external rfsx with mce = 1, mfd = 0 12 10 ns t dtenlfse 1, 2 data enable from late fs or mce = 1, mfd = 0 0 0 ns 1 mce = 1, tfsx enable and tfsx valid follow t ddtenfs and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2 then t ddtte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfs apply. figure 24. external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 41 of 68 | january 2011 serial peripheral interface (spi) portmaster timing table 37 and figure 25 describe spi port master operations. table 37. serial peripheral interface (spi) portmaster timing v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 11.6 9.6 ns t hspidm sck sampling edge to data input invalid C1.5 C1.5 ns switching characteristics t sdscim spiselx low to first sck edge 2 t sclk C1.5 2 t sclk C1.5 ns t spichm serial clock high period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclm serial clock low period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk 4 t sclk ns t hdsm last sck edge to spiselx high 2 t sclk C1.5 2 t sclk C1.5 ns t spitdm sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 6 6 ns t hdspidm sck edge to data out invalid (data out hold) C1 C1 ns figure 25. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
rev. b | page 42 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f serial peripheral interface (spi) portslave timing table 38 and figure 26 describe spi port slave operations. universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-bf51x hardware reference manual . table 38. serial peripheral interface (spi) portslave timing v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 4 t sclk C1.5 ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk C1.5 2 t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 1.6 ns t hspid sck sampling edge to data input invalid 2 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 12 0 10.3 ns t dsdhi spiss deassertion to data high impedance 0 11 0 9 ns t ddspid sck edge to data out valid (data out delay) 10 10 ns t hdspid sck edge to data out invalid (data out hold) 0 0 ns figure 26. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 43 of 68 | january 2011 general-purpose port timing table 39 and figure 27 describe general-purpose port operations. timer clock timing table 40 and figure 28 describe timer clock timing. table 39. general-purpose port timing v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing requirement t wfi general-purpose port signal input pulse width t sclk + 1 t sclk + 1 ns switching characteristics t gpod general-purpose port signal output delay from clkout low 0 11 0 8.5 ns figure 27. general-purpose port timing clkout gpio output gpio input t wfi t gpod table 40. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppiclk high 12 ns figure 28. timer clock timing ppi_clk tmrx output t todp
rev. b | page 44 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f timer cycle timing table 41 and figure 29 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 41. timer cycle timing v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter min max min max unit timing characteristics t wl 1 timer pulse width input low (measured in sclk cycles) t sclk t sclk ns t wh 1 timer pulse width input high (measured in sclk cycles) t sclk t sclk ns t tis 2 timer input setup time before clkout low 10 7 ns t tih 2 timer input hold time after clkout low C2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) t sclk C 1.5 (2 32 C1)t sclk t sclk C 1 (2 32 C1)t sclk ns t tod timer output update delay after clkout high 6 6 ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock mode s. they also apply to the pf15 or ppi_c lk signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 29. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 45 of 68 | january 2011 up/down counter/rotary encoder timing 10/100 ethernet mac controller timing table 43 through table 48 and figure 31 through figure 36 describe the 10/100 ethernet mac cont roller operations. table 42. up/down counter/rotary encoder timing parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t wcount up/down counter/rotary encoder input pulse width t sclk + 1 t sclk + 1 ns t cis counter input setup time before clkout low 1 1 either a valid setup and hold time or a valid pulse width is su fficient. there is no need to resynchronize counter inputs. 97 ns t cih counter input hold time after clkout low 1 00 ns figure 30. up/down counter/rotary encoder timing clkout cud/cdg/czm t cis t cih t wcount table 43. 10/100 ethernet mac controll er timing: mii receive signal v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter 1 min max min max unit timing requirements t erxclkf erxclk frequency (f sclk = sclk frequency) none 25 + 1% none 25 + 1% mhz t erxclkw erxclk width (t erxclk = erxclk period) t erxclk x 40% t erxclk x 60% t erxclk x 35% t erxclk x 65% ns t erxclkis rx input valid to erxclk rising edge (data in setup) 7.5 7.5 ns t erxclkih erxclk rising edge to rx input invalid (data in hold) 7.5 7.5 ns 1 mii inputs synchronous to erxclk are erxd3C0, erxdv, and erxer. figure 31. 10/100 ethernet mac controller timing: mii receive signal t erxclkis t erxclkih erxd3C0 erxdv erxer erx_clk t erxclkw t erxclk
rev. b | page 46 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table 44. 10/100 ethernet mac controll er timing: mii transmit signal v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter 1 min max min max unit switching characteristics t etf etxclk frequency (f sclk = sclk frequency) none 25 + 1% none 25 + 1% mhz t etxclkw etxclk width (t etxclk = etxclk period) t etxclk 40% t etxclk 60% t etxclk 35% t etxclk 65% ns t etxclkov etxclk rising edge to tx output valid (data out valid) 20 20 ns t etxclkoh etxclk rising edge to tx output invalid (data out hold) 0 0 ns 1 mii outputs synchronous to etxclk are etxd3C0. figure 32. 10/100 ethernet mac controller timing: mii transmit signal table 45. 10/100 ethernet mac controll er timing: rmii receive signal v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal parameter 1 minmax minmax unit timing requirements t erefclkf ref_clk frequency (f sclk = sclk frequency) none 50 + 1% none 50 + 1% mhz t erefclkw eref_clk width (t erefclk = erefclk period) t erefclk 40% t erefclk 60% t erefclk 35% t erefclk 65% ns t erefclkis rx input valid to rmii ref_clk rising edge (data in setup) 44ns t erefclkih rmii ref_clk rising edge to rx input invalid (data in hold) 22ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. figure 33. 10/100 ethernet mac controller timing: rmii receive signal t etxclkoh etxd3C0 etxen miitxclk t etxclk t etxclkov t etxclkw t refclkis t refclkih erxd1C0 erxdv erxer rmii_ref_clk t refclkw t refclk
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 47 of 68 | january 2011 table 46. 10/100 ethernet mac controller timing: rmii transmit signal parameter 1 min max unit switching characteristics t erefclkov rmii ref_clk rising edge to tx output valid (data out valid) 8.1 ns t erefclkoh rmii ref_clk rising edge to tx output invalid (data out hold) 2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. figure 34. 10/100 ethernet mac controller timing: rmii transmit signal t refclkov t refclkoh rmii_ref_clk etxd1C0 etxen t refclk
rev. b | page 48 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table 47. 10/100 ethernet mac controller timing: mii/rmii asynchronous signal parameter min max unit timing requirements t ecolh col pulse width high 1 t etxclk 1.5 t erxclk 1.5 ns ns t ecoll col pulse width low 1 t etxclk 1.5 t erxclk 1.5 ns ns t ecrsh crs pulse width high 2 t etxclk 1.5 ns t ecrsl crs pulse width low 2 t etxclk 1.5 ns 1 mii/rmii asynchronous signals are col, crs. these signals are appl icable in both mii and rmii modes. the asynchronous col input is synchronized se parately to both the etxclk and the erxclk, and must have a minimum pulse width high or low at least 1.5 times the period of the sl ower of the t wo clocks. 2 the asynchronous crs input is synchronized to the etxclk, and mus t have a minimum pulse width high or low at least 1.5 times th e period of etxclk. figure 35. 10/100 ethernet mac controller timing: asynchronous signal table 48. 10/100 ethernet mac controller timing: mii station management parameter 1 min max unit timing requirements t mdios mdio input valid to mdc rising edge (setup) 11.5 ns t mdcih mdc rising edge to mdio input invalid (hold) 0 ns switching characteristics t mdcov mdc falling edge to md io output valid 25 ns t mdcoh mdc falling edge to mdio ou tput invalid (hold) C1.25 ns 1 mdc/mdio is a 2-wire serial bidirectional port for controlling one or more external phys. mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk. mdio is a bidirectional data line. figure 36. 10/100 ethernet mac contro ller timing: mii station management miicrs, col t ecrsh t ecolh t ecrsl t ecoll mdio (input) mdio (output) mdc (output) t mdios t mdcoh t mdcih t mdcov
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 49 of 68 | january 2011 jtag test and emulation port timing table 49 and figure 37 describe jtag port operations. table 49. jtag port timing parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys 1 system inputs setup before tck high 4 ns t hsys 1 system inputs hold after tck high 5 ns t trstw trst pulse width 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys 3 system outputs delay after tck low 0 13 ns 1 system inputs = data15C0, scl, sda, tfs0, tsclk0, rsclk0, rfs0, dr0pri, dr0sec, pf15C0, pg15C0, ph7C0, mdio, td1, tms, reset , nmi , bmode2C0. 2 50 mhz maximum 3 system outputs = data15C0, addr19C1, abe1C0 , are , awe , ams1C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec, pf15C0, pg15C0, ph7C0, mdc, mdio. figure 37. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. b | page 50 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f output drive currents figure 38 through figure 52 show typical current-voltage char- acteristics for the output drivers of the adsp-bf51xf processors. the curves represent the current drive capability of the output drivers. see table 7 on page 17 for information about which driver type correspond s to a particular ball. figure 38. driver type a current (3.3v v ddext /v ddmem ) figure 39. driver type a current (2.5v v ddext /v ddmem ) figure 40. driver type a current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 200 120 80 C200 C120 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C160 40 160 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 160 120 40 C160 C120 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C80 v ddext = 2.25v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 80 60 40 C80 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c figure 41. driver type b current (3.3v v ddext /v ddmem ) figure 42. driver type b current (2.5v v ddext /v ddmem ) figure 43. driver type b current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 240 120 80 C240 C120 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C200 40 160 v ddext = 3.0v @ 105 c C160 200 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 160 120 40 C200 C160 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C80 v ddext = 2.25v @ 105 c C120 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 80 60 40 C100 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c C80
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 51 of 68 | january 2011 figure 44. driver type c current (3.3v v ddext /v ddmem ) figure 45. drive type c current (2.5v v ddext /v ddmem ) figure 46. driver type c current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 60 40 C100 C60 C20 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C40 C80 20 80 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 80 60 20 C80 C60 C20 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 40 C40 v ddext = 2.25v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 40 30 20 C40 C30 C10 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C20 10 v ddext = 1.7v @ 105 c figure 47. driver type d current (3.3v v ddext /v ddmem ) figure 48. driver type d current (2.5v v ddext /v ddmem ) figure 49. driver type d current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 160 120 80 C160 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C120 40 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 120 100 40 C120 C100 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C60 v ddext = 2.25v @ 105 c C80 C20 20 60 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2 60 40 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c
rev. b | page 52 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 53 shows the measurement point for ac measurements (except out- put enable/disable). the measurement point v meas is v ddext /2 or v ddmem /2 for v ddext /v ddmem (nominal) = 1.8 v/2.5 v/3.3 v. output enable time measurement output signals are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 54 . the time t ena_measured is the interval from when the reference signal switches to when the output voltage reaches v trip (high) or v trip (low). for v ddext (nominal) = 1.8 v, v trip (high) is 0.95 v, and v trip (low) is 0.85 v. for v ddext (nominal) = 2.5 v, v trip (high) is 1.3 v and v trip (low) is 1.2 v. for v ddext (nomi- nal) = 3.3 v, v trip (high) is 1.7 v, and v trip (low) is 1.6 v. time t trip is the interval from when the output starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as sh own in the equation: if multiple signals (such as the data bus) are enabled, the mea- surement value is that of the first signal to start driving. figure 50. driver type e current (3.3v v ddext /v ddmem ) figure 51. driver type e current (2.5v v ddext /v ddmem ) figure 52. driver type e current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 60 30 20 C60 C30 C10 v ol v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C20 C40 10 40 v ddext = 3.0v @ 105 c 50 C50 3.0 3.5 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 40 30 10 C40 C30 C10 v ol v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 20 C20 v ddext = 2.25v @ 105 c 3.5 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 20 15 10 C20 C15 C5 v ol v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C10 5 v ddext = 1.7v @ 105 c 3.0 2.5 2.0 figure 53. voltage reference levels for ac measurements (except output enable/disable) figure 54. output enable/disable input or output v meas v meas reference signal t dis output starts driving v oh (measured) - v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low) t ena t ena_measured t trip ? =
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 53 of 68 | january 2011 output disable time measurement output signals are considered to be disabled when they stop driving, go into a hi gh impedance state, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis_measured and t decay as shown on the left side of figure 54 . the time for the voltage on the bus to decay by v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l and with v equal to 0.25 v for v ddext /v ddmem (nominal) = 2.5 v/3.3 v and 0.15 v for v ddext / vddmem (nominal) = 1.8 v. the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the adsp-bf51x processors out- put voltage and the input threshol d for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time is t decay plus the various output disable times as specified in the timing specifications on page 27 (for example t dsdat for an sdram write cycle as shown in sdram interface timing on page 31 ). capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all balls (see figure 55 ). v load is equal to (v ddext /v ddmem )/2. the graphs of figure 56 through figure 67 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figure s. the graphs in these figures may not be linear outside the ranges shown. t dis t dis_measured t decay ? = t decay c l v () i l ? = figure 55. equivalent device loading for ac measurements (includes all fixtures) figure 56. driver type a typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to reflect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 6 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 12 10 0 2 4 8 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c
rev. b | page 54 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f figure 57. driver type a typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 58. driver type a typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 59. driver type b typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 8 6 0 1 2 5 200 t rise t fall 3 7 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 3 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 6 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 9 7 0 1 3 6 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 2 5 8 figure 60. driver type b typical rise and fall times (10C90) vs. load capacitance (2.5v v ddext /v ddmem ) figure 61. driver type b typical rise and fall times (10C90) vs. load capacitance (3.3v v ddext /v ddmem ) figure 62. driver type c typical rise and fall times (10C90) vs. load capacitance (1.8v v ddext /v ddmem ) 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 7 6 0 1 2 5 200 t rise t fall 3 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 3 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 6 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 15 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 25 20 0 5 10 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 55 of 68 | january 2011 figure 63. driver type c typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 64. driver type c typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 65. driver type d typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 8 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 16 12 0 2 4 10 200 t rise t fall 6 14 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 6 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 14 12 0 2 4 8 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 10 6 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 14 10 0 2 4 8 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 12 figure 66. driver type d typical rise and fall times (10C90) vs. load capacitance (2.5v v ddext /v ddmem ) figure 67. driver type d typical rise and fall times (10C90) vs. load capacitance (3.3v v ddext /v ddmem ) 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 10 6 0 1 2 5 200 t rise t fall 3 7 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 8 9 3 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 8 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 6 7
rev. b | page 56 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f thermal characteristics to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) measured by customer at top center of package. jt = from table 51 p d = power dissipation (see total power dissipation on page 23 for the method to calculate p d ) values of ja are provided for package comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. values of jb are provided for package comparison and printed circuit board design considerations. in table 51 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. the lqfp_ep package requires th ermal trace squares and ther- mal vias to an embedded ground plane in the pcb. the paddle must be connected to ground for proper operation to data sheet specifications. refer to jedec standard jesd51-5 for more information. t j t case jt p d () + = t j t a ja p d () + = table 50. thermal characteristics for sq-176-2 package parameter condition typical unit ja 0 linear m/s airflow 17.4 c/w jma 1 linear m/s airflow 14.8 c/w jma 2 linear m/s airflow 14.0 c/w jc not applicable 7.8 c/w jt 0 linear m/s airflow 0.28 c/w jt 1 linear m/s airflow 0.39 c/w jt 2 linear m/s airflow 0.48 c/w table 51. thermal characteri stics for bc-168-1 package parameter condition typical unit ja 0 linear m/s airflow 30.5 c/w jma 1 linear m/s airflow 27.6 c/w jma 2 linear m/s airflow 26.3 c/w jc not applicable 11.1 c/w jt 0 linear m/s airflow 0.20 c/w jt 1 linear m/s airflow 0.35 c/w jt 2 linear m/s airflow 0.45 c/w
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 57 of 68 | january 2011 176-lead lqfp lead assignment table 52 lists the lqfp leads by lead number. table 53 on page 58 lists the lqfp by signal mnemonic. table 52. 176-lead lqfp pin assignme nt (numerical by lead number) lead no. signal lead no. signal lead no. signal lead no. signal 1 gnd 45 gnd 89 gnd 133 gnd 2 gnd 46 gnd 90 gnd 134 gnd 3 pf9 47 pg1 91 a12 135 pg 4 pf8 48 pg0 92 a11 136 v ddext 5pf749v ddext 93 a10 137 gnd 6pf650tdo94a9138v ddint 7v ddext 51 emu 95 v ddmem 139 gnd 8v ppotp 52 tdi 96 a8 140 rtxo 9v ddotp 53 tck 97 a7 141 rtxi 10 pf5 54 trst 98 v ddint 142 v ddrtc 11 pf4 55 tms 99 gnd 143 clkin 12 pf3 56 d15 100 v ddint 144 xtal 13 pf2 57 d14 101 a6 145 v ddext 14 v ddint 58 d13 102 a5 146 reset 15 gnd 59 v ddmem 103 a4 147 nmi 16 v ddflash 60 d12 104 v ddmem 148 v ddext 17 v ddflash 61 d11 105 a3 149 gnd 18 pf1 62 d10 106 a2 150 clkbuf 19 pf0 63 v ddint 107 a1 151 gnd 20 pg15 64 d9 108 abe 1152 v ddint 21 pg14 65 d8 109 abe 0153 ph7 22 gnd 66 d7 110 sa10 154 ph6 23 v ddint 67 gnd 111 gnd 155 ph5 24 v ddext 68 v ddmem 112 v ddmem 156 ph4 25 pg13 69 d6 113 swe 157 gnd 26 pg12 70 d5 114 scas 158 v ddext 27 pg11 71 d4 115 sras 159 ph3 28 pg10 72 d3 116 v ddint 160 ph2 29 v ddflash 73 d2 117 gnd 161 ph1 30 v ddint 74 d1 118 sms 162 ph0 31 pg9 75 v ddmem 119 scke 163 gnd 32 pg8 76 d0 120 ams 1164 v ddint 33 pg7 77 a19 121 are 165 pf15 34 pg6 78 a18 122 awe 166 pf14 35 v ddext 79 v ddint 123 ams 0167 pf13 36 pg5 80 a17 124 v ddmem 168 pf12 37 pg4 81 a16 125 clkout 169 gnd 38 pg3 82 v ddmem 126 v ddflash 170 v ddext 39 pg2 83 gnd 127 nc 1 171 pf11 40 bmode2 84 a15 128 v ddext 172 sda 41 bmode1 85 a14 129 v ddext 173 scl 42 bmode0 86 a13 130 ext_wake 174 pf10 43 gnd 87 gnd 131 gnd 175 gnd 44 gnd 88 gnd 132 gnd 176 gnd gnd 177 * * pin no. 177 is the gnd supply (see figure 69 ) for the processor; this pad must connect to gnd. 1 this pin must not be connected.
rev. b | page 58 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f table 53. 176-lead lqfp pin assignment (alphabetica l by signal mnemonic) lead no. signal lead no. signal lead no. signal lead no. signal 107 a1 58 d13 5 pf7 113 swe 106 a2 57 d14 4 pf8 53 tck 105 a3 56 d15 3 pf9 52 tdi 103 a4 51 emu 174 pf10 50 tdo 102 a5 130 ext_wake 171 pf11 55 tms 101 a6 1 gnd 168 pf12 54 trst 97 a7 2 gnd 167 pf13 7 v ddext 96 a8 15 gnd 166 pf14 24 v ddext 94 a9 22 gnd 165 pf15 35 v ddext 93 a10 43 gnd 135 pg 49 v ddext 92 a11 44 gnd 48 pg0 128 v ddext 91 a12 45 gnd 47 pg1 129 v ddext 86 a13 46 gnd 39 pg2 136 v ddext 85 a14 67 gnd 38 pg3 145 v ddext 84 a15 83 gnd 37 pg4 148 v ddext 81 a16 87 gnd 36 pg5 158 v ddext 80 a17 88 gnd 34 pg6 170 v ddext 78 a18 89 gnd 33 pg7 16 v ddflash 77 a19 90 gnd 32 pg8 17 v ddflash 109 abe 099gnd31pg929v ddflash 108 abe 1 111 gnd 28 pg10 126 v ddflash 123 ams 0131gnd27pg1114v ddint 120 ams 1132gnd26pg1223v ddint 121 are 133 gnd 25 pg13 30 v ddint 122 awe 134 gnd 21 pg14 63 v ddint 42 bmode0 137 gnd 20 pg15 79 v ddint 41 bmode1 139 gnd 162 ph0 98 v ddint 40 bmode2 149 gnd 161 ph1 100 v ddint 150 clkbuf 151 gnd 160 ph2 116 v ddint 143 clkin 157 gnd 159 ph3 138 v ddint 125 clkout 163 gnd 156 ph4 152 v ddint 76 d0 169 gnd 155 ph5 164 v ddint 74 d1 175 gnd 154 ph6 59 v ddmem 73 d2 176 gnd 153 ph7 68 v ddmem 72 d3 117 gnd 146 reset 75 v ddmem 71 d4 127 nc 1 141 rtxi 82 v ddmem 70 d5 147 nmi 140 rtxo 95 v ddmem 69 d6 19 pf0 110 sa10 104 v ddmem 66 d7 18 pf1 114 scas 112 v ddmem 65 d8 13 pf2 119 scke 124 v ddmem 64 d9 12 pf3 173 scl 9 v ddotp 62 d10 11 pf4 172 sda 142 v ddrtc 61 d11 10 pf5 118 sms 8v ppotp 60 d12 6 pf6 115 sras 144 xtal gnd 177 * * pin no. 177 is the gnd supply (see figure 69 ) for the processor; this pad must connect to gnd. 1 this pin must not be connected.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 59 of 68 | january 2011 figure 68 shows the top view of the lqfp_ep lead configura- tion. figure 69 shows the bottom view of the lqfp_ep lead configuration. figure 68. 176-lead lqfp_ep lead configuration (top view) pin 1 pin 44 pin 1 3 2 pin 8 9 pin 176 pin 1 33 pin 45 pin 88 pin 1 indicator ad s p-bf51x 176-lead lqfp_ep top view figure 69. 176-lead lqfp_ep lead configuration (bottom view) pin 1 3 2 pin 8 9 pin 1 pin 44 pin 1 33 pin 176 pin 88 pin 45 pin 1 indicator ad s p-bf51x 176-lead lqfp_ep bottom view gnd pad (pin 177)
rev. b | page 60 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f 168-ball csp_bga ball assignment table 54 lists the csp_bga by ball number. table 55 on page 61 lists the csp_bga balls by signal mnemonic. table 54. 168-ball csp_bga ball assign ment (numerical by ball number) ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name a1 gnd c1 pf4 e10 v ddint h1 pg12 k6 v ddmem n1 bmode1 a2 scl c2 pf7 e12 v ddmem h2 pg13 k7 v ddmem n2 pg1 a3 sda c3 pf8 e13 are h3 pg11 k8 v ddmem n3 tdo a4 pf13 c4 pf10 e14 awe h5 v ddext k9 v ddmem n4 trst a5 pf15 c5 v ddext f1 pf0 h6 gnd k10 v ddmem n5 tms a6 ph2 c6 v ddext f2 pf1 h7 gnd k12 a8 n6 d13 a7 ph1 c7 pf11 f3 v ddint h8 gnd k13 a2 n7 d9 a8 ph5 c8 v ddext f5 v ddext h9 gnd k14 a1 n8 d5 a9 ph6 c9 v ddint f6 gnd h10 v ddint l1 pg5 n9 d1 a10 ph7 c10 v ddext f7 gnd h12 a3 l2 pg3 n10 a18 a11 clkbuf c11 rtxi f8 gnd h13 abe 0l3pg2 n11a16 a12 xtal c12 rtxo f9 gnd h14 scas l12 a9 n12 a14 a13 clkin c13 pg f10 v ddint j1 pg10 l13 a6 n13 a11 a14 gnd c14 nc 1 f12 sms j2 v ddflash l14 a4 n14 a7 b1 v ddotp d1 pf3 f13 scke j3 pg9 m1 pg4 p1 gnd b2 gnd d2 pf5 f14 ams 1j5v ddmem m2 bmode2 p2 tdi b3 pf9 d3 vppotp g1 pg15 j6 gnd m3 bmode0 p3 tck b4 pf12 d12 v ddflash g2 pg14 j7 gnd m4 pg0 p4 d15 b5 pf14 d13 clkout g3 v ddint j8 gnd m5 emu p5 d14 b6 ph0 d14 ams 0g5v ddext j9 gnd m6 d12 p6 d11 b7 ph3 e1 v ddflash g6 gnd j10 v ddint m7 d10 p7 d8 b8 ph4 e2 pf2 g7 gnd j12 a15 m8 d2 p8 d7 b9 v ddext e3 pf6 g8 gnd j13 abe 1m9d0 p9d6 b10 reset e5 v ddext g9 gnd j14 sa10 m10 a17 p10 d4 b11 nmi e6 v ddext g10 v ddint k1 pg6 m11 a13 p11 d3 b12 v ddrtc e7 v ddint g12 swe k2 pg8 m12 a12 p12 a19 b13 v ddext e8 v ddint g13 sras k3 pg7 m13 a10 p13 gnd b14 ext_wake e9 v ddint g14 gnd k5 v ddmem m14 a5 p14 gnd 1 this pin must not be connected.
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 61 of 68 | january 2011 table 55. 168-ball csp_bga ball assignment (alphabetical by signal mnemonic) ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name k14 a1 a11 clkbuf g6 gnd c4 pf10 a8 ph5 g5 v ddext k13 a2 a13 clkin g7 gnd c7 pf11 a9 ph6 h5 v ddext h12 a3 d13 clkout g8 gnd b4 pf12 a10 ph7 d12 v ddflash l14 a4 m9 d0 g9 gnd a4 pf13 b10 reset e1 v ddflash m14 a5 n9 d1 h6 gnd b5 pf14 c11 rtxi j2 v ddflash l13 a6 m8 d2 h7 gnd a5 pf15 c12 rtxo c9 v ddint n14 a7 p11 d3 h8 gnd c13 pg j14 sa10 e7 v ddint k12 a8 p10 d4 h9 gnd m4 pg0 h14 scas e8 v ddint l12 a9 n8 d5 j6 gnd n2 pg1 f13 scke e9 v ddint m13 a10 p9 d6 j7 gnd l3 pg2 a2 scl e10 v ddint n13 a11 p8 d7 j8 gnd l2 pg3 a3 sda f3 v ddint m12 a12 p7 d8 j9 gnd m1 pg4 f12 sms f10 v ddint m11 a13 n7 d9 p1 gnd l1 pg5 g13 sras g3 v ddint n12 a14 m7 d10 p13 gnd k1 pg6 g12 swe g10 v ddint j12 a15 p6 d11 p14 gnd k3 pg7 p3 tck h10 v ddint n11 a16 m6 d12 g14 gnd k2 pg8 p2 tdi j10 v ddint m10 a17 n6 d13 c14 nc 1 j3 pg9 n3 tdo e12 v ddmem n10 a18 p5 d14 b11 nmi j1 pg10 n5 tms j5 v ddmem p12 a19 p4 d15 f1 pf0 h3 pg11 n4 trst k5 v ddmem h13 abe 0m5emu f2 pf1 h1 pg12 b9 v ddext k6 v ddmem j13 abe 1 b14 ext_wake e2 pf2 h2 pg13 b13 v ddext k7 v ddmem d14 ams 0a1gnd d1pf3 g2pg14 c5v ddext k8 v ddmem f14 ams 1 a14 gnd c1 pf4 g1 pg15 c6 v ddext k9 v ddmem e13 are b2 gnd d2 pf5 b6 ph0 c8 v ddext k10 v ddmem e14 awe f6 gnd e3 pf6 a7 ph1 c10 v ddext b1 v ddotp m3 bmode0 f7 gnd c2 pf7 a6 ph2 e5 v ddext b12 v ddrtc n1 bmode1 f8 gnd c3 pf8 b7 ph3 e6 v ddext d3 v ppotp m2 bmode2 f9 gnd b3 pf9 b8 ph4 f5 v ddext a12 xtal 1 this pin must not be connected.
rev. b | page 62 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f figure 70 shows the top view of the csp_bga ball configura- tion. figure 71 shows the bottom view of the csp_bga ball configuration. figure 70. 168-ball csp_bga ba ll configuration (top view) figure 71. 168-ball csp_bga ball configuration (bottom view) a1 ball pad corner top view a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11121314 v ddint v ddext gnd i/o key v ddrtc v ddmem v ddflash nc a1 ball pad corner bottom view a b c d e f g h j k l m n p 1413121110987654321 v ddint v ddext gnd i/o key v ddrtc v ddmem v ddflash nc
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 63 of 68 | january 2011 outline dimensions dimensions in figure 72 are shown in millimeters. figure 72. 176-lead low profile quad flat package [lqfp_ep] (sq-176-2) dimensions shown in millimeters compliant to jedec standards ms-026-bga-hd 1.45 1.40 1.35 0.15 0.10 0.05 top view (pins down) 133 1 132 45 44 88 89 176 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 26.20 26.00 sq 25.80 24.10 24.00 sq 23.90 view a pin 1 0.08 max coplanarity view a rotated 90 ccw seating plane 12 7 0 0.20 0.15 0.09 0.75 0.60 0.45 1.00 ref bottom view (pins up) 133 1 132 45 44 88 89 176 exposed pad exposed pad is centered on the package. 5.80 ref sq note: the exposed pad is required to be electrically and thermally connected to gnd. implement this by soldering the exposed pad to a gnd pcb land that is the same size as the exposed pad. the gnd pcb land should be robustly connected to the gnd plane in the pcb with an array of thermal vias for best performance.
rev. b | page 64 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f surface-mount design table 56 is provided as an aid to pcb design. for industry standard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . figure 73. 168-ball chip scale package ball grid array [csp_bga] (bc-168-1) dimensions shown in millimeters 0.80 bsc 10.40 bsc sq 12.10 12.00 sq 11.90 compliant to jedec standards mo-275-ggab-1. 0.80 ref 0.70 ref 0.36 ref a b c d e f g 910 8 1112 7 5 64231 bottom view h j k l m detail a top view detail a coplanarity 0.20 0.50 0.45 0.40 ball diameter seating plane a1 ball corner a1 ball corner 0.34 nom 0.29 min 1.50 1.40 1.30 1.12 1.06 1.00 14 13 n p table 56. bga data for use with surface-mount design package package ball attach type package solder mask opening package ball pad size 168-ball csp_bga solder mask defined 0.35 mm diameter 0.48 mm diameter
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 65 of 68 | january 2011 automotive products the adbf512w and ad bf518 models are available with con- trolled manufacturing to suppor t the quality and reliability requirements of automotive appl ications. note that these auto- motive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. only the auto- motive grade products shown in table 57 are available for use in automotive applications. contac t your local adi account repre- sentative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ordering guide table 57. automotive products automotive models 1,2 temperature range 3 instruction rate (max) package description package option adbf512wbbcz4xx C40oc to +85oc 400 mhz 168-ball csp_bga bc-168-1 adbf518wbbcz4xx C40oc to +85oc 400 mhz 168-ball csp_bga bc-168-1 adbf512wbswz4xx C40oc to +85oc 400 mhz 176-lead lqfp_ep sq-176-2 adbf518wbswz4xx C40oc to +85oc 400 mhz 176-lead lqfp_ep sq-176-2 1 z = rohs compliant part. 2 the use of xx designates silicon revision. 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 20 for junction temperature (t j ) specification which is the on ly temperature specification. model 1 temperature range 2 processor instruction rate (max) flash memory package description package option adsp-bf512bbcz-3 C40oc to +85oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf512bbcz-4 C40oc to +85oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf512bbcz-4f4 C40oc to +85oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf512bswz-3 C40oc to +85oc 300 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf512bswz-4 C40oc to +85oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf512bswz-4f4 C40oc to +85oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf512kbcz-3 0oc to +70oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf512kbcz-4 0oc to +70oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf512kbcz-4f4 0oc to +70oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 ADSP-BF512KSWZ-3 0oc to +70oc 300 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf512kswz-4 0oc to +70oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf512kswz-4f4 0oc to +70oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf514bbcz-3 C40oc to +85oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf514bbcz-4 C40oc to +85oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf514bbcz-4f4 C40oc to +85oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf514bswz-3 C40oc to +85oc 300 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf514bswz-4 C40oc to +85oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf514bswz-4f4 C40oc to +85oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf514kbcz-3 0oc to +70oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf514kbcz-4 0oc to +70oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf514kbcz-4f4 0oc to +70oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf514kswz-3 0oc to +70oc 300 mhz n/a 176-lead lqfp_ep sq-176-2
rev. b | page 66 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f adsp-bf514kswz-4 0oc to +70oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf514kswz-4f4 0oc to +70oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf516kswz-3 0oc to +70oc 300 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf516kbcz-3 0oc to +70oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf516kswz-4 0oc to +70oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf516kbcz-4 0oc to +70oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf516kswz-4f4 0oc to +70oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf516kbcz-4f4 0oc to +70oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf516bbcz-3 C40oc to +85oc 300 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf516bbcz-4 C40oc to +85oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf516bbcz-4f4 C40oc to +85oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf516bswz-3 C40oc to +85oc 300 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf516bswz-4 C40oc to +85oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf516bswz-4f4 C40oc to +85oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 adsp-bf518bbcz-4 C40oc to +85oc 400 mhz n/a 168-ball csp_bga bc-168-1 adsp-bf518bbcz-4f4 C40oc to +85oc 400 mhz 4m bit 168-ball csp_bga bc-168-1 adsp-bf518bswz-4 C40oc to +85oc 400 mhz n/a 176-lead lqfp_ep sq-176-2 adsp-bf518bswz-4f4 C40oc to +85oc 400 mhz 4m bit 176-lead lqfp_ep sq-176-2 1 z = rohs compliant part. 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 20 for junction temperature (t j ) specification which is the on ly temperature specification. model 1 temperature range 2 processor instruction rate (max) flash memory package description package option
adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f rev. b | page 67 of 68 | january 2011
rev. b | page 68 of 68 | january 2011 adsp-bf512/bf512f, bf514/bf514f, bf516/bf516f, bf518/bf518f ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08574-0-1/11(b)

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